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參數(shù)資料
| 型號： | MC74HCT241AN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal 3-State Noninverting Buffer/Line Driver/Line Receiver with LSTTL-Compatible Inputs |
| 中文描述： | HCT SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDIP20 |
| 封裝： | PLASTIC, DIP-20 |
| 文件頁數(shù)： | 4/7頁 |
| 文件大?。?/td> | 148K |
| 代理商： | MC74HCT241AN |
MC54/74HCT241A
MOTOROLA
High–Speed CMOS Logic Data
DL129 — Rev 6
4
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Symbol
b l
Parameter
U i
10
15
25 C
– 55 to
85 C
125 C
pF
pF
(Figures 2 and 4)
tPHL
(Figures 1 and 3)
tPZH
Maximum Propagation Delay, Output Enable to YA or YB
30
38
45
ns
(Figures 1 and 3)
Maximum Input Capacitance
Cout
Maximum Three–State Output Capacitance (Output in High–Impedance
tTHL
Maximum Output Transition Time, Any Output
12
15
18
10
10
15
15
CPD
Power Dissipation Capacitance (Per Enabled Output)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
bl d O
Typical @ 25
°
C, VCC = 5.0 V
55
pF
SWITCHING WAVEFORMS
Figure 1.
Figure 2.
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 3. Test Circuit
* Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 4. Test Circuit
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
1 k
ENABLE A
ENABLE B
OUTPUT Y
OUTPUT Y
3 V
GND
3 V
GND
HIGH
IMPEDANCE
HIGH
IMPEDANCE
VOL
VOH
1.3 V
1.3 V
1.3 V
1.3 V
90%
10%
tPZL
tPLZ
tPZH
tPHZ
3 V
GND
tf
tr
INPUT
A OR B
OUTPUT
YA OR YB
0.3 V
2.7 V
10%
190%
tTLH
tPLH
tPHL
tTHL
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