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參數(shù)資料
| 型號(hào)： | MC74HCT74AN |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 通用總線功能 |
| 英文描述： | Quad 2-Input NAND Gate with LSTTL-Compatible Inputs |
| 中文描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | PLASTIC, DIP-14 |
| 文件頁(yè)數(shù)： | 3/5頁(yè) |
| 文件大?。?/td> | 172K |
| 代理商： | MC74HCT74AN |
MC54/74HCT00A
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
or B to Output Y
tTHL
Time, Any Output
Cin
NOTE:For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Maximum Input Capacitance
—
10
10
10
pF
CPD
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25
°
C, VCC = 5.0 V
15
pF
Figure 1. Switching Waveforms
tf
tr
3.0 V
GND
90%
1.3 V
10%
90%
1.3 V
10%
INPUT
A OR B
OUTPUT Y
tPHL
tPLH
tTLH
tTHL
* Includes all probe and jig capacitance
Figure 2. Test Circuit
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
EXPANDED LOGIC DIAGRAM
(1/4 OF THE DEVICE)
Y
A
B
3
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