參數(shù)資料
型號(hào): MC74LCX16240ADTR2
廠商: ON SEMICONDUCTOR
元件分類: 總線收發(fā)器
英文描述: LVC/LCX/Z SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48
封裝: PLASTIC, TSSOP-48
文件頁(yè)數(shù): 21/40頁(yè)
文件大小: 327K
代理商: MC74LCX16240ADTR2
Design Considerations
LCX DATA
BR1339 — REV 3
25
MOTOROLA
Local high frequency decoupling is required to supply
power to the chip when it is transitioning from a LOW to a HIGH
value. This power is necessary to charge the load capacitance
or drive a line impedance. Figure 22 displays various VCC and
ground layout schemes along with associated impedances.
For most power distribution networks, the typical impedance
is between 100 and 150
. This impedance appears in series
with the load impedance and will cause a droop in the VCC at
the part. This limits the available voltage swing at the local
node, unless some form of decoupling is used. This drooping
of rails will cause the rise and fall times to become elongated.
Consider the example described in Figure 23 to calculate the
amount of decoupling necessary. This circuit utilizes an
LCX240 driving a 150
bus from a point somewhere in the
middle.
DATA BUS
150
BUFFER
1 OF 8
100 V
GROUND
PLANE
VOUT
0.1V
IOH
0
2.9 V
4.0ns
37mA
Worst–Case Octal Drain = 8
× 37mA = 0.3 Amp.
Figure 23. Octal Buffer Driving a 150
Bus
Buffer Output Sees Net 75
Load.
75
Load Line on IOH–VOH Characteristic
Shows Low–to–High Step of Approx. 2.8V
Being in the middle of the bus, the driver will see two 150
loads in parallel, or an effective impedance of 75
. To switch
the line from rail to rail, a drive of 37mA is needed; about
300mA will be required if all eight lines switch at once. This
instantaneous current requirement will generate a voltage
across the impedance of the power lines, causing the actual
VCC at the chip to droop. This droop limits the voltage swing
available to the driver. The net effect of the voltage droop will
lengthen device rise and fall times and slow system operation.
A local decoupling capacitor is required to act as a low
impedance supply for the driver chip during high current
conditions. It will maintain the voltage within acceptable limits
and keep rise and fall times to a minimum. The necessary
values for decoupling capacitors can be calculated with the
formula given in Figure 24.
In this example, if the VCC droop is to be kept below 30mV
and the edge rate equals 4 ns, a 0.04
F capacitor is needed.
It is good practice to distribute decoupling capacitors
evenly through the logic, placing one capacitor for every
package.
Capacitor Types
Decoupling capacitors need to be of the high K ceramic
type with low equivalent series resistance (ESR), consisting
primarily of series inductance and series resistance.
Capacitors using 5ZU dielectric have suitable properties and
make a good choice for decoupling capacitors; they offer
minimum cost and effective performance.
Figure 24. Formula for Calculating Decoupling Capacitors
VCC BUS
VCC
ZCC
CB
BYPASS CAPACITORS
SPECIFY VCC DROOP = 30mV MAX.
I = 0.3A
Q = CV
I = C
V/t
C = I
t/V
t = 4 × 10 –9
C =
0.30
× 4 × 10–9
0.03
= 40
× 10–9 = 0.040 F
SELECT CB ≥ 0.047 F
Place one decoupling capacitor adjacent to each package
driving any transmission line and distribute others evenly
throughout the logic.
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