SEMICONDUCTOR TECHNICAL DATA
1
REV 2
Motorola, Inc. 1996
11/96
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The MC74LCX646 is a high performance, non–inverting octal
transceiver/registered transceiver operating from a 2.7 to 3.6V supply.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5V allows
MC74LCX646 inputs to be safely driven from 5V devices. The
MC74LCX646 is suitable for memory address driving and all TTL level
bus oriented transceiver applications.
Data on the A or B bus will be clocked into the registers as the
appropriate clock pin goes from a LOW–to–HIGH logic level. Output
Enable (OE) and DIR pins are provided to control the transceiver outputs.
In the transceiver mode, data present at the high impedance port may be
stored in either the A or the B register or in both. The select controls (SBA,
SAB) can multiplex stored and real–time (transparent mode) data. The
direction control (DIR) determines which bus will receive data when the
enable OE is active LOW. In the isolation mode (OE HIGH), A data may
be stored in the B register or B data may be stored in the A register. Only
one of the two buses, A or B, may be driven at one time.
Designed for 2.7 to 3.6V VCC Operation
5V Tolerant — Interface Capability With 5V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0V
LVTTL Compatible
LVCMOS Compatible
24mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10
μ
A)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 500mA
ESD Performance: Human Body Model >2000V; Machine Model >200V
Pinout: 24–Lead Package
(Top View)
23
24
22
21
20
19
18
2
1
3
4
5
6
7
VCC
17
8
16
9
15
10
CBA
SBA
OE
B0
B1
B2
B3
B4
B5
CAB
SAB
DIR
A0
A1
A2
A3
A4
A5
A6
14
11
13
12
B6
B7
A7
GND
DW SUFFIX
PLASTIC SOIC
CASE 751E–04
DT SUFFIX
PLASTIC TSSOP
CASE 948H–01
24
1
24
1
SD SUFFIX
PLASTIC SSOP
CASE 940D–03
24
1
LOW–VOLTAGE CMOS
OCTAL TRANSCEIVER/
REGISTERED TRANSCEIVER
PIN NAMES
Function
Side A Inputs/Outputs
Side B Inputs/Outputs
Clock Pulse Inputs
Select Control Inputs
Output Enable Inputs
Pins
A0–A7
B0–B7
CAB, CBA
SAB, SBA
DIR, OE