參數(shù)資料
型號: MC74LVX125D
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: LOW-VOLTAGE CMOS
中文描述: LV/LV-A/LVX/H SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14
封裝: PLASTIC, SOIC-14
文件頁數(shù): 1/6頁
文件大?。?/td> 147K
代理商: MC74LVX125D
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1997
6/97
" " "
! ! "!
The MC74LVX125 is an advanced high speed CMOS quad bus buffer.
The inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
The MC74LVX125 requires the 3–state control input (OE) to be set
High to place the output into the high impedance state.
High Speed: tPD = 4.4ns (Typ) at VCC = 3.3V
Low Power Dissipation: ICC = 4
μ
A (Max) at TA = 25
°
C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Low Noise: VOLP = 0.5V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Figure 1. 14–Lead Pinout
(Top View)
13
14
12
11
10
9
8
2
1
3
4
5
6
7
VCC
OE3
D3
O3
OE2
D2
O2
OE0
D0
O0
OE1
D1
O1
GND
D0
2
O0
3
OE0
1
D1
5
O1
6
OE1
4
D2
9
O2
8
OE2
10
D3
12
O3
11
OE3
13
Figure 2. Logic Diagram
LOW–VOLTAGE CMOS
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
PIN NAMES
Function
Output Enable Inputs
Data Inputs
3–State Outputs
Pins
OEn
Dn
On
H = High Voltage Level; L = Low Voltage Level; Z = High Imped-
ance State; X = High or Low Voltage Level and Transitions Are
Acceptable, for ICC reasons, DO NOT FLOAT Inputs
OEn
Dn
On
L
L
H
L
H
X
L
H
Z
INPUTS
OUTPUTS
FUNCTION TABLE
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