參數(shù)資料
型號(hào): MC74VHC02DTR2G
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/5頁(yè)
文件大?。?/td> 0K
描述: IC GATE NOR QUAD 2INPUT 14-TSSOP
標(biāo)準(zhǔn)包裝: 2,500
系列: 74VHC
邏輯類(lèi)型: 或非門(mén)
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.5V
邏輯電平 - 高: 1.5V
額定電壓和最大 CL 時(shí)的最大傳播延遲: 7.5ns @ 5V,50pF
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
供應(yīng)商設(shè)備封裝: 14-TSSOP
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 帶卷 (TR)
其它名稱(chēng): MC74VHC02DTR2G-ND
MC74VHC02DTR2GOSTR
Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 5
1
Publication Order Number:
MC74VHC02/D
MC74VHC02
Quad 2-Input NOR Gate
The MC74VHC02 is an advanced high speed CMOS 2input NOR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
Figure 1. LOGIC DIAGRAM
1
Y1
2
A1
3
B1
Y4
Y = A + B
4
Y2
5
A2
6
B2
10
Y3
8
A3
9
B3
13
11
A4
12
B4
TSSOP14
DT SUFFIX
CASE 948G
http://onsemi.com
1
VHC02G
AWLYWW
1
14
SOIC14
D SUFFIX
CASE 751A
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
1
VHC
02
ALYW G
G
1
14
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G = PbFree Package
(Note: Microdot may be in either location)
FUNCTION TABLE
A
L
H
Inputs
Output
B
L
H
L
H
Y
H
L
11
12
13
14
8
9
10
5
4
3
2
1
7
6
Y3
A4
B4
Y4
VCC
A3
B3
Y2
B1
A1
Y1
GND
B2
A2
PIN ASSIGNMENT
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