參數(shù)資料
型號: MC74VHC08DTR2G
廠商: ON Semiconductor
文件頁數(shù): 1/7頁
文件大?。?/td> 0K
描述: IC GATE AND QUAD 2INPUT 14-TSSOP
標準包裝: 1
系列: 74VHC
邏輯類型: 與門
電路數(shù): 4
輸入數(shù): 2
電源電壓: 2 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 2µA
輸出電流高,低: 8mA,8mA
邏輯電平 - 低: 0.5V
邏輯電平 - 高: 1.5V
額定電壓和最大 CL 時的最大傳播延遲: 7.9ns @ 5V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應商設備封裝: 14-TSSOP
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
包裝: 標準包裝
其它名稱: MC74VHC08DTR2GOSDKR
Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 8
1
Publication Order Number:
MC74VHC08/D
MC74VHC08
Quad 2-Input AND Gate
The MC74VHC08 is an advanced high speed CMOS 2input AND
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 4.3 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300 mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 24 FETs or 6 Equivalent Gates
These Devices are PbFree and are RoHS Compliant
3
Y1
1
A1
Figure 1. Logic Diagram
2
B1
6
Y2
4
A2
5
B2
8
Y3
9
A3
10
B3
11
Y4
12
A4
13
B4
Y = AB
Figure 2. Pinout: 14Lead Packages
13
14
12
11
10
9
8
2
1
34567
VCC
B4
A4
Y4
B3
A3
Y3
A1
B1
Y1
A2
B2
Y2
GND
(Top View)
SOIC14
D SUFFIX
CASE 751A
TSSOP
DT SUFFIX
CASE 948G
SOEIAJ14
M SUFFIX
CASE 965
http://onsemi.com
(Note: Microdot may be in either location)
MARKING
DIAGRAMS
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
L
H
Y
VHC
08
ALYW G
G
1
14
1
14
74VHC08
ALYWG
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or G = PbFree Package
1
14
VHC08G
AWLYWW
1
14
1
14
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