參數(shù)資料
型號: MC74VHC1G135DFT1
廠商: ON Semiconductor
文件頁數(shù): 1/6頁
文件大小: 0K
描述: IC GATE NAND SGL 2INP OD SOT-353
產(chǎn)品變化通告: LTB Notification 03/Jan/2008
標準包裝: 3,000
系列: 74VHC
邏輯類型: 與非門
電路數(shù): 1
輸入數(shù): 2
特點: 施密特觸發(fā)器,開路漏極
電源電壓: 2 V ~ 5.5 V
電流 - 靜態(tài)(最大值): 1µA
輸出電流高,低: -,8mA
邏輯電平 - 低: 0.65 V ~ 1.45 V
邏輯電平 - 高: 2.25 V ~ 3.7 V
額定電壓和最大 CL 時的最大傳播延遲: 9.7ns @ 4.5V ~ 5.5V,50pF
工作溫度: -55°C ~ 125°C
安裝類型: 表面貼裝
供應商設備封裝: SC-70
封裝/外殼: 6-TSSOP(5 引線),SC-88A,SOT-353
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2010
April, 2010 Rev. 16
1
Publication Order Number:
MC74VHC1G135/D
MC74VHC1G135
2-Input NAND
Schmitt-Trigger with
Open Drain Output
The MC74VHC1G135 is a single gate CMOS Schmitt NAND
trigger with an open drain output fabricated with silicon gate CMOS
technology. It achieves high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining CMOS low power
dissipation.
The internal circuit is composed of three stages, including an open
drain output which provides the capability to set the output switching
level. This allows the MC74VHC1G135 to be used to interface 5 V
circuits to circuits of any voltage between VCC and 7 V using an
external resistor and power supply.
The MC74VHC1G135 input structure provides protection when
voltages up to 7 V are applied, regardless of the supply voltage.
The MC74VHC1G135 can be used to enhance noise immunity or to
square up slowly changing waveforms.
Features
High Speed: tPD = 4.9 ns (Typ) at VCC = 5 V
Low Internal Power Dissipation: ICC = 1 mA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 70; Equivalent Gates = 18
PbFree Packages are Available
Figure 1. Pinout (Top View)
5
1
2
4
3
VCC
IN B
IN A
OUT Y
GND
IN A
IN B
OUT Y
&
OVT
Figure 2. Logic Symbol
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
L
H
L
H
L
H
FUNCTION TABLE
Inputs
Output
AB
Z
L
Y
PIN ASSIGNMENT
1
2
3
GND
IN B
IN A
4
5VCC
OUT Y
SC88A/SOT353/SC70
DF SUFFIX
CASE 419A
TSOP5/SOT23/SC59
DT SUFFIX
CASE 483
MARKING
DIAGRAMS
1
5
1
5
1
5
VZ M G
G
VZ
= Device Code
M
= Date Code*
G
= PbFree Package
(Note: Microdot may be in either location)
*Date Code orientation and/or position may vary
depending upon manufacturing location.
1
5
VZ M G
G
M
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