參數(shù)資料
型號: MC7805ECT
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 基準電壓源/電流源
英文描述: 5.0 AMP POSITIVE VOLTAGE REGULATOR
中文描述: 5 V FIXED POSITIVE REGULATOR, SFM3
封裝: TO-220, 3 PIN
文件頁數(shù): 4/8頁
文件大?。?/td> 129K
代理商: MC7805ECT
MC141622EVK
4
MOTOROLA
4.2 Clock Generator Compounding
The clock generator (MC1378P) provides the necessary reference oscillator and phase locks the clock to
the color subcarrier by inputting the composite video signal.
VC1 adjusts the horizontal VCO to synchronize the output of the burst gate (pin 5 on the MC1378P) with
the input video signal. VC2 adjusts the chroma VCO for maximum amplitude output from the clock buffer
(pin 1 on the MC14576).
VR3 adjusts pull–in of the chroma PLL filter. This is usually fixed to the center position. VR4 selects the
dc bias for the clock buffer output and is usually 2.25 V.
4.3 Video Amplifier Adjustment
On the video amplifier (MC14577), the gain is adjusted by VR1. This sets the input range
(3.0 Vp–p) of the A/D converter in MC141622FU.
VR2 is the clamp level adjustment. This adjusts the sync tip clamping of the input video signal to the
video amplifier.
4.4 Outside Interface
The outside interface should provide a composite video input signal to BNC1. The MC141622EVK pro-
vides Y/C separation and outputs the luminance from BNC2 and the color signal from BNC3. There is an
S output connector on this board for easy connection to instruments having an S input connector.
BNC4 and BNC5 are for the external input of each CLK and CLK(AD). However, when using these, it is
necessary to modify the board pattern; i.e., cut (J5, J6).
There is no filter for bandwidth limitations on this board beyond that imposed by the bandwidth limitations
of the MC14577 buffer amplifier. To minimize noise resulting from excessive bandwidth, the bandwidth of
input video signal should be limited to no more than one half of the clock frequency.
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