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參數(shù)資料
| 型號： | MC7HC273A |
| 廠商： | Motorola, Inc. |
| 英文描述： | Octal D Flip-Flop with Common Clock and Reset |
| 中文描述： | 八路D觸發(fā)器與普通時鐘和復位拖鞋 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 184K |
| 代理商： | MC7HC273A |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 7
Motorola, Inc. 1997
2/97
!
High–Performance Silicon–Gate CMOS
The MC54/74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of eight D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active low.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 264 FETs or 66 Equivalent Gates
LOGIC DIAGRAM
DATA
INPUTS
D0
11
CLOCK
D1
D2
D3
D4
D5
D6
D7
18
17
14
13
8
7
4
3
1
RESET
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
16
15
12
9
6
5
2
PIN 20 = VCC
PIN 10 = GND
NONINVERTING
OUTPUTS
Internal Gate Power Dissipation
Design Criteria
Value
Units
* Equivalent to a two–input NAND gate.
.0075
pJ
5.0
μ
W
Speed Power Product
PIN ASSIGNMENT
Q2
D1
D0
Q0
RESET
GND
Q3
D3
D2
Q1
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
11
12
13
Q6
D6
D7
Q7
VCC
CLOCK
Q4
D4
D5
Q5
FUNCTION TABLE
Inputs
Clock
Output
Q
Reset
D
L
H
H
H
H
X
X
H
L
X
X
L
H
L
L
No Change
No Change
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
1
20
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