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| 型號(hào)： | MC80C52CXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 文件頁(yè)數(shù)： | 68/80頁(yè) |
| 文件大?。?/td> | 5152K |
| 代理商： | MC80C52CXXX-12SB |
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268
XMEGA A [MANUAL]
8077I–AVR–11/2012
Table 24-2. SDRAM Interface signals
24.7.1 Supported Commands
The SDRAM commands that are supported by the EBI is listed in Table 24-3 on page 268.
Table 24-3. Supported SDRAM commands.
24.7.2 Three-Port EBI Configuration
When three EBI ports are available, SDRAM can be connected with a three-Port EBI configuration. When this is done
only four-bit data bus is available, and any chip select must be controlled from software using a general purpose I/O pin
(Pxn).
Signal
Description
CS
Chip select
WE
Write enable
RAS
Row address strobe
CAS
Column address strobe
DQM
Data mask signal/ output enable
CKE
Clock enable
CLK
Clock
BA[1:0]
Bank address
A[12:0]
Address bus
A[10]
Precharge
D[7:0]
Data bus
Command
Description
NOP
No Operation
ACTIVE
Activate the selected bank and select the row
READ
Input the starting column address and begin the burst read operation
WRITE
Input the starting column address and begin the burst write operation
PRECHARGE
Deactivate the open row of selected bank or all banks
AUTO REFRESH
Refresh one row of each bank
LOAD MODE
Load mode register
SELF REFRESH
Activate self refresh mode
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