參數(shù)資料
型號: MC80C52TXXX-25SC
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù): 21/109頁
文件大小: 10824K
代理商: MC80C52TXXX-25SC
24
AT32UC3A
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
9.2.6
Unimplemented instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
All SIMD instructions
All coprocessor instructions
retj, incjosp, popjc, pushjc
tlbr, tlbs, tlbw
cache
9.2.7
CPU and Architecture revision
Two major revisions of the AVR32UC CPU currently exist. The device described in this
datasheet uses CPU revision 2.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 2 is fully backward-compatible with revision 1, ie. code compiled for
revision 1 is binary-compatible with revision 2 CPUs.
Table 9-1.
Instructions with unaligned reference support
Instruction
Supported alignment
ld.d
Word
st.d
Word
32058K
AVR32-01/12
相關(guān)PDF資料
PDF描述
MC80C32-30SHXXX:D 8-BIT, 30 MHz, MICROCONTROLLER, CDIP40
MQ80C52CXXX-25:R 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44
MD80C52TXXX-20P883D 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40
MQ80C32-20P883D 8-BIT, 20 MHz, MICROCONTROLLER, CQFP44
MD80C52CXXX-30SB 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CDIP40
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