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| 型號： | MC8640TVU1250HC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 83/130頁 |
| 文件大小： | 0K |
| 描述： | MPU DUAL E600 994-FCCBGA |
| 標準包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.25GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 994-BCBGA，F(xiàn)CCBGA |
| 供應商設備封裝： | 994-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
56
Freescale Semiconductor
I
2C
Figure 36. I2C AC Test Load
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2
× OVDD
—V
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the
high (H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition
(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When MPC8640 acts as the I2C bus master while transmitting, MPC8640 drives both SCL and SDA. As long as the load on
SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start or Stop condition. Therefore, the 300
ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for
MPC8640 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the
desired I2C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I2C SCL clock frequency
is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal
16):
I2C Source Clock Frequency
333 MHz
266 MHz
200 MHz
133 MHz
FDR Bit Setting
0x2A
0x05
0x26
0x00
Actual FDR Divider Selected
896
704
512
384
Actual I2C SCL Frequency Generated
371 KHz
378 KHz
390 KHz
346 KHz
For the detail of I2C frequency calculation, refer to the application note AN2919 “Determining the I2C Frequency Divider Ratio
for SCL.” Note that the I2C Source Clock Frequency is half of the MPX clock frequency for MPC8640.
3. The maximum tI2DXKL has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
4. Guaranteed by design.
5. CB = capacitance of one bus line in pF.
Table 46. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 45).
Parameter
Symbol1
Min
Max
Unit
Output
Z0 = 50 Ω
OVDD/2
RL = 50 Ω
相關PDF資料 |
PDF描述 |
|---|---|
| 345-012-542-204 | CARDEDGE 12POS DUAL .100 GREEN |
| MC8640TVU1067NC | MPU DUAL E600 994-FCCBGA |
| 345-012-542-202 | CARDEDGE 12POS DUAL .100 GREEN |
| 345-012-542-201 | CARDEDGE 12POS DUAL .100 GREEN |
| MPC8533EVTANG | MPU POWERQUICC 783-PBGA |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MC8640TVU1250HE | 功能描述:微處理器 - MPU G8 REV3.0 0.95V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640TVU1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8640xTxxyyyyaC Series |
| MC8640VU1000H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications |
| MC8640VU1000HC | 功能描述:微處理器 - MPU G8 REV2.1 1.05V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC8640VU1000HE | 功能描述:微處理器 - MPU G8 REV 3.0 1.05V 105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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