參數(shù)資料
型號： MC8641DTHX1250HE
廠商： Freescale Semiconductor
文件頁數(shù)： 96/130頁
文件大?。?/td> 0K
描述： IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.25GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 1023-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 1023-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
68
Freescale Semiconductor
High-Speed Serial Interfaces (HSSI)
13.2.4
AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise
occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50
Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
Table 47 describes some AC parameters common to PCI Express and Serial RapidIO protocols.
Figure 47. Differential Measurement Points for Rise and Fall Time
Table 47. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS1 or XVDD_SRDS2 = 1.1V ± 5% and 1.05V ± 5%.
Parameter
Symbol
Min
Max
Unit
Notes
Rising Edge Rate
Rise Edge Rate
1.0
4.0
V/ns
2, 3
Falling Edge Rate
Fall Edge Rate
1.0
4.0
V/ns
2, 3
Differential Input High Voltage
VIH
+200
mV
2
Differential Input Low Voltage
VIL
—
–200
mV
2
Rising edge rate (SD
n_REF_CLK) to falling edge rate
(SD
n_REF_CLK) matching
Rise-Fall
Matching
—20
%
1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD
n_REF_CLK minus SDn_REF_CLK). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered
on the differential zero crossing. See Figure 47.
4. Matching applies to rising edge rate for SD
n_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a 200
mV window centered on the median cross point where SDn_REF_CLK rising meets SD
n_REF_CLK falling. The median cross
point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate
of SD
n_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 48.
VIH = +200 mV
VIL = -200 mV
0.0 V
SD
n_REF_CLK
minus
SD
n_REF_CLK
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