參數(shù)資料
型號: MC8641DTHX1333JE
廠商: Freescale Semiconductor
文件頁數(shù): 10/130頁
文件大?。?/td> 0K
描述: IC DUAL CORE PROCESSOR 1023-CBGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC86xx
處理器類型: 32-位 MPC86xx PowerPC
速度: 1.333GHz
電壓: 1.05V
安裝類型: 表面貼裝
封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
包裝: 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
Freescale Semiconductor
107
Clocking
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also note
that the DDR data rate is the determining factor in selecting the MPX bus frequency, since the MPX
frequency must equal the DDR data rate.
18.3
e600 to MPX clock PLL Ratio
Table 69 describes the clock ratio between the platform and the e600 core clock. This ratio is determined
by the binary value of LDP[0:3], LA[27](cfg_core_pll[0:4] - reset config name) at power up, as shown in
18.4
Frequency Options
Table 68. MPX:SYSCLK Ratio
Binary Value of LA[28:31] Signals
MPX:SYSCLK Ratio
0000
Reserved
0001
Reserved
0010
2:1
0011
3:1
0100
4:1
0101
5:1
0110
6:1
0111
Reserved
1000
8:1
1001
9:1
Table 69. e600 Core to MPX Clock Ratio
Binary Value of LDP[0:3], LA[27] Signals
e600 core: MPX Clock Ratio
01000
2:1
01100
2.5:1
10000
3:1
11100
3.5:1
10100
4:1
01110
4.5:1
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