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| 型號： | MC8641DTVU1250HE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 66/130頁 |
| 文件大小： | 0K |
| 描述： | IC MPU DUAL CORE E600 1023FCCBGA |
| 標準包裝： | 1 |
| 系列： | MPC86xx |
| 處理器類型： | 32-位 MPC86xx PowerPC |
| 速度： | 1.25GHz |
| 電壓： | 1.05V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 1023-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 1023-FCCBGA（33x33） |
| 包裝： | 托盤 |
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MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
40
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 19 shows the RGMII and RTBI AC timing and multiplexing diagrams.
Figure 19. RGMII and RTBI AC Timing and Multiplexing Diagrams
Clock period duration 3
tRGT
5,6
7.2
8.0
8.8
ns
Duty cycle for 10BASE-T and 100BASE-TX 3, 4
tRGTH/tRGT
5
40
50
60
%
Rise time (20%–80%)
tRGTR
5
—
0.75
ns
Fall time (80%–20%)
tRGTF
5
—
0.75
ns
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. For example, the subscript of tRGT represents the TBI (T) receive (RX) clock. Note also that the
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the
subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned
between.
5. Guaranteed by characterization
6. ±100 ppm tolerance on RX_CLK frequency
Table 35. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
GTX_CLK
tRGT
tRGTH
tSKRGT
TX_CTL
TXD[8:5]
TXD[7:4]
TXD[9]
TXERR
TXD[4]
TXEN
TXD[3:0]
(At Transmitter)
TXD[8:5][3:0]
TXD[7:4][3:0]
TX_CLK
(At PHY)
RX_CTL
RXD[8:5]
RXD[7:4]
RXD[9]
RXERR
RXD[4]
RXDV
RXD[3:0]
RXD[8:5][3:0]
RXD[7:4][3:0]
RX_CLK
(At PHY)
tSKRGT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC8641DTVU1250J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1250N | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1333G | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1333H | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
| MC8641DTVU1333J | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Host Processor Hardware Specifications Addendum for the MC8641xTxxnnnnxC Series |
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