• 參數(shù)資料
    型號: MC8641DVU1000GB
    廠商: Freescale Semiconductor
    文件頁數(shù): 114/130頁
    文件大小: 0K
    描述: IC MPU DUAL E600 CORE 1023FCCBGA
    標準包裝: 1
    系列: MPC86xx
    處理器類型: 32-位 MPC86xx PowerPC
    速度: 1.0GHz
    電壓: 1.05V
    安裝類型: 表面貼裝
    封裝/外殼: 1023-BCBGA,F(xiàn)CCBGA
    供應(yīng)商設(shè)備封裝: 1023-FCCBGA(33x33)
    包裝: 托盤
    MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
    84
    Freescale Semiconductor
    Serial RapidIO
    Table 60. Receiver AC Timing Specifications—2.5 GBaud
    Characteristic
    Symbol
    Range
    Unit
    Notes
    Min
    Max
    Differential Input Voltage
    VIN
    200
    1600
    mV p-p
    Measured at receiver
    Deterministic Jitter Tolerance
    JD
    0.37
    UI p-p
    Measured at receiver
    Combined Deterministic and Random
    Jitter Tolerance
    JDR
    0.55
    UI p-p
    Measured at receiver
    Total Jitter Tolerance1
    JT
    0.65
    UI p-p
    Measured at receiver
    Multiple Input Skew
    SMI
    24
    ns
    Skew at the receiver input
    between lanes of a multilane
    link
    Bit Error Rate
    BER
    10–12
    ——
    Unit Interval
    UI
    400
    ps
    +/– 100 ppm
    Note:
    1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
    sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component
    is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
    Table 61. Receiver AC Timing Specifications—3.125 GBaud
    Characteristic
    Symbol
    Range
    Unit
    Notes
    Min
    Max
    Differential Input Voltage
    VIN
    200
    1600
    mV p-p
    Measured at receiver
    Deterministic Jitter Tolerance
    JD
    0.37
    UI p-p
    Measured at receiver
    Combined Deterministic and Random
    Jitter Tolerance
    JDR
    0.55
    UI p-p
    Measured at receiver
    Total Jitter Tolerance1
    JT
    0.65
    UI p-p
    Measured at receiver
    Multiple Input Skew
    SMI
    22
    ns
    Skew at the receiver input
    between lanes of a multilane
    link
    Bit Error Rate
    BER
    10-12
    ——
    Unit Interval
    UI
    320
    ps
    +/– 100 ppm
    Note:
    1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
    sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 55. The sinusoidal jitter component
    is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
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