1.         
      
      
      參數(shù)資料
      型號: MC8641DVU1000HB
      廠商: FREESCALE SEMICONDUCTOR INC
      元件分類: 微控制器/微處理器
      英文描述: MICROPROCESSOR, CBGA1023
      封裝: 33 X 33 MM, ROHS COMPLIANT, CERAMIC, BGA-1023
      文件頁數(shù): 14/140頁
      文件大?。?/td> 1484K
      代理商: MC8641DVU1000HB
      MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 0
      110
      Freescale Semiconductor
      Clocking
      18.1
      Clock Ranges
      Table 64 provides the clocking specifications for the processor cores and Table 65 provides the clocking
      specifications for the memory bus. Table 66 provides the clocking for the Platform/MPX bus and Table 67
      provides the clocking for the Local bus.
      Table 64. Processor Core Clocking Specifications
      Characteristic
      Maximum Processor Core Frequency
      Unit
      Notes
      1000 MHz
      1250MHz
      1333MHz
      1500 MHz
      Min
      Max
      Min
      Max
      Min
      Max
      Min
      Max
      e600 core processor frequency
      800
      1000
      800
      1250
      800
      1333
      800
      1500
      MHz
      1, 2
      Notes:
      1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
      SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
      for ratio settings.
      2. The minimum e600 core frequency is based on the minimum platform clock frequency of 400 MHz.
      Table 65. Memory Bus Clocking Specifications
      Characteristic
      Maximum Processor Core
      Frequency
      Unit
      Notes
      1000, 1250, 1333, 1500MHz
      Min
      Max
      Memory bus clock frequency
      200
      300
      MHz
      1, 2
      Notes:
      1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be
      chosen such that the resulting SYSCLK frequency, e600 (core) frequency, and MPX clock
      frequency do not exceed their respective maximum or minimum operating frequencies. Refer to
      ratio settings.
      2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock
      frequency.
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