參數(shù)資料
型號： MC8641TVU1333JC
廠商： Freescale Semiconductor
文件頁數(shù)： 59/130頁
文件大小： 0K
描述： MPU E600 SGL CORE 994-FCCBGA
標(biāo)準(zhǔn)包裝： 1
系列： MPC86xx
處理器類型： 32-位 MPC86xx PowerPC
速度： 1.333GHz
電壓： 1.05V
安裝類型： 表面貼裝
封裝/外殼： 994-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 994-FCCBGA（33x33）
包裝： 托盤
MPC8641 and MPC8641D Integrated Host Processor Hardware Specifications, Rev. 2
34
Freescale Semiconductor
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Figure 11 provides the AC test load for eTSEC.
Figure 11. eTSEC AC Test Load
Figure 12 shows the GMII receive AC timing diagram.
Figure 12. GMII Receive AC Timing Diagram
RX_CLK clock fall time (80%-20%)
tGRXF
2
——
1.0
ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII
receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock
reference (K) going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to
the time data input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time.
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
3. ±100 ppm tolerance on RX_CLK frequency
Table 29. GMII Receive AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5% and 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Output
LVDD/2
RL = 50 Ω
Z0 = 50 Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKH
RX_DV
RX_ER
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