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參數(shù)資料
| 型號： | MC88915 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Skew CMOS PLL Clock Driver |
| 中文描述： | 低偏移的CMOS PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 216K |
| 代理商： | MC88915 |
MC88915TFN55/70/100/133/160
TIMING SOLUTIONS
BR1333 — Rev 6
7
MOTOROLA
MC88915TFN100
(continued)
AC CHARACTERISTICS
(TA =–40
°
C to +85
°
C, VCC = 5.0V
±
5%, Load = 50
Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2VCC and 0.8VCC)
1.0
2.5
ns
Into a 50
Load
Terminated to VCC/2
tRISE/FALL
1
2X_Q Output
Rise/Fall Time Into a 20pF Load, With
Termination Specified in Note
2
0.5
1.6
ns
tRISE: 0.8V – 2.0V
tFALL: 2.0V – 0.8V
tPULSE WIDTH
1
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5
2
0.5tCYCLE + 0.5
2
ns
Into a 50
Load
Terminated to VCC/2
tPULSE WIDTH
1
(2X_Q Output)
Output Pulse Width:
2X_Q @ 1.5V
0.5tCYCLE – 0.5
2
0.5tCYCLE + 0.5
2
ns
Must Use Termination
Specified in Note
2
tPULSE WIDTH
1
(2X_Q Output)
Output Pulse Width:
2X_Q @ VCC/2
40–49MHz
50–65MHz
66–100MHz
0.5tCYCLE – 1.5
2
0.5tCYCLE – 1.0
0.5tCYCLE – 0.5
0.5tCYCLE + 1.5
2
0.5tCYCLE + 1.0
0.5tCYCLE + 0.5
ns
Into a 50
Load
Terminated to VCC/2
tPD
1,3
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
(With 1M
from RC1 to An VCC)
ns
See Note
4
and
Figure 2 for Detailed
Explanation
p a a o
–1.05
–0.30
(With 1M
from RC1 to An GND)
+1.25
+3.25
tSKEWr
1,4
(Rising) See Note
5
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWf
1,4
(Falling)
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWall
1,4
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
—
750
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tLOCK
5
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL
6
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
tPHZ,tPLZ
6
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
1. These specifications are not tested, they are guaranteed by statistcal characterization. See AC specification Note 1.
2. TCYCLE in this spec is 1/Frequency at which the particular output is running.
3. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
4. Under equally loaded conditions and at a fixed temperature and voltage.
5. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1
μ
F, tLOCK minimum is
with C1 = 0.01
μ
F.
6. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
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