參數(shù)資料
型號(hào)： MC88915FN55
廠商： MOTOROLA INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： Low Skew CMOS PLL Clock Driver
中文描述： 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封裝： PLASTIC, LCC-28
文件頁數(shù)： 16/20頁
文件大?。?/td> 216K
代理商： MC88915FN55
MC88915TFN55/70/100/133/160
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
16
Figure 5c. Wiring Diagram and Frequency Relationships with 2X_Q Output Feed Back
Figure 5b. Wiring Diagram and Frequency Relationships With Q4 Output Feed Back
Figure 5a. Wiring Diagram and Frequency Relationships With Q/2 Output Feed Back
Q4
Q4
Q5
Allowable Input Frequency Range:
20MHz to (2X_Q FMAX Spec)
(for FREQ_SEL HIGH)
10MHz to (2X_Q FMAX Spec)/2
(for FREQ_SEL LOW)
Allowable Input Frequency Range:
10MHz to (2X_Q FMAX Spec)/2
(for FREQ_SEL HIGH)
5MHz to (2X_Q FMAX Spec)/4
(for FREQ_SEL LOW)
In this application, the 2X_Q output is connected
to the FEEDBACK input. The internal PLL will line
up the positive edges of 2X_Q and SYNC, thus the
2X_Q frequency will equal the SYNC frequency.
The Q/2 output will always run at 1/4 the 2X_Q fre-
quency, and the “Q” outputs will run at 1/2 the
2X_Q frequency.
2:1 Input to “Q” Output Frequency Relationship
In this application, the Q4 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q4 and SYNC, thus the Q4
frequency (and the rest of the “Q” outputs) will
equal the SYNC frequency. The Q/2 output will al-
ways run at 1/2 the “Q” frequency, and the 2X_Q
output will run at 2X the “Q” frequency.
1:1 Input to “Q” Output Frequency Relationship
Allowable Input Frequency Range:
5MHz to (2X_Q FMAX Spec)/4
(for FREQ_SEL HIGH)
2.5MHz to (2X_Q FMAX Spec)/8
(for FREQ_SEL LOW)
In this application, the Q/2 output is connected to
the FEEDBACK input. The internal PLL will line up
the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The “Q”
outputs (Q0–Q4, Q5) will always run at 2X the Q/2
frequency, and the 2X_Q output will run at 4X the
Q/2 frequency.
1:2 Input to “Q” Output Frequency Relationship
50MHz FEEDBACK SIGNAL
HIGH
25MHz FEEDBACK SIGNAL
HIGH
25MHz
SIGNAL
25MHz
SIGNAL
100MHz FEEDBACK SIGNAL
HIGH
2X_Q
Q/2
ANALOG VCC
RC1
CRYSTAL
OSCILLATOR
100MHz INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
MC88915T
EXTERNAL
LOOP
FILTER
100MHz SIGNAL
2X_Q
Q/2
ANALOG VCC
RC1
CRYSTAL
OSCILLATOR
50MHZ INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
MC88915T
EXTERNAL
LOOP
FILTER
100MHz SIGNAL
2X_Q
Q/2
ANALOG VCC
RC1
50MHz
“Q”
CLOCK
OUTPUTS
CRYSTAL
OSCILLATOR
25MHz INPUT
HIGH
LOW
HIGH
PLL_EN
FQ_SEL
Q0
Q1
Q2
Q3
Q4
RST
FEEDBACK
REF_SEL
SYNC[0]
ANALOG GND
MC88915T
Q5
Q5
EXTERNAL
LOOP
FILTER
50MHz
“Q”
CLOCK
OUTPUTS
50MHz
“Q”
CLOCK
OUTPUTS
Note: If the OE/RST input is active, a pull–up or pull–down re-
sistor isn’t necessary at the FEEDBACK pin so it won’t when
the fed back output goes into 3–state.
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MC88915FN55PLCC 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low Skew CMOS PLL Clock Driver
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MC88915FN70 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
MC88915FN70PLCC 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low Skew CMOS PLL Clock Driver
MC88915FN70R2 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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