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參數(shù)資料
| 型號： | MC88915FN55PLCC |
| 廠商： | Motorola, Inc. |
| 英文描述： | Low Skew CMOS PLL Clock Driver |
| 中文描述： | 低偏移的CMOS PLL時(shí)鐘驅(qū)動器 |
| 文件頁數(shù)： | 18/20頁 |
| 文件大小： | 216K |
| 代理商： | MC88915FN55PLCC |
MC88915TFN55/70/100/133/160
MOTOROLA
TIMING SOLUTIONS
BR1333 — Rev 6
18
MC88915T System Level Testing Functionality
3–state functionality has been added to the 100MHz version of the MC88915T to ease system board testing. Bringing the
OE/RST pin low will put all outputs (except for LOCK) into the high impedance state. As long as the PLL_EN pin is low, the
Q0–Q4, Q5, and the Q/2 outputs will remain reset in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q
output will be the inverse of the SYNC signal in this mode. If the 3–state functionality will be used, a pull–up or pull–down resistor
must be tied to the FEEDBACK input pin to prevent it from floating when the fedback output goes into high impedance.
With the PLL_EN pin low the selected SYNC signal is gated directly into the internal clock distribution network, bypassing
and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can
also be used for low frequency board testing.
Note: If the outputs are put into 3–state during normal PLL operation, the loop will be broken and phase–lock will be lost. It will
take a maximum of 10mS (tLOCK spec) to regain phase–lock after the OE/RST pin goes back high.
Figure 7. Representation of a Potential Multi–Processing Application Utilizing the MC88915T
for Frequency Multiplication and Low Board–to–Board Skew
MC88915T
PLL
2f
2f
MC88915T
PLL
SYSTEM
CLOCK
SOURCE
CPU
CARD
CPU
CARD
MEMORY
CARDS
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
CLOCK
@ f
CMMU
CMMU
CMMU
CMMU
CMMU
CPU
2f
PLL
MEMORY
CONTROL
CLOCK @ 2f
AT POINT OF USE
CLOCK @ 2f
AT POINT OF USE
DISTRIBUTE
CLOCK @ f
MC88915T
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC88915T | LOW SKEW CMOS PLL CLOCK DRIVER |
| MC88915TFN133 | CONNECTOR ACCESSORY |
| MC88915TFN160 | LOW SKEW CMOS PLL CLOCK DRIVER |
| MC88915TFN55 | CONNECTOR ACCESSORY |
| MC88915TFN70 | CONNECTOR ACCESSORY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC88915FN55R2 | 功能描述:IC DRIVER CLK PLL 55MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915FN70 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915FN70PLCC | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Low Skew CMOS PLL Clock Driver |
| MC88915FN70R2 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88915T | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER |
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