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參數(shù)資料
| 型號： | MC88915TFN160 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER |
| 中文描述： | 88915 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大小： | 216K |
| 代理商： | MC88915TFN160 |
MC88915TFN55/70/100/133/160
TIMING SOLUTIONS
BR1333 — Rev 6
11
MOTOROLA
MC88915TFN160
(continued)
AC CHARACTERISTICS
(TA =0
°
C to +70
°
C, VCC = 5.0V
±
5%, Load = 50
Terminated to VCC/2)
Symbol
Parameter
Min
Max
Unit
Condition
tRISE/FALL
Outputs
Rise/Fall Time, All Outputs
(Between 0.2VCC and 0.8VCC)
1.0
2.5
ns
Into a 50
Load
Terminated to VCC/2
tRISE/FALL
2X_Q Output
Rise/Fall Time
0.5
1.6
ns
tRISE: 0.8V – 2.0V
tFALL: 2.0V – 0.8V
tPULSE WIDTH
(Q0–Q4, Q5, Q/2)
Output Pulse Width: Q0, Q1, Q2, Q3,
Q4, Q5, Q/2 @ VCC/2
0.5tCYCLE – 0.5
2
0.5tCYCLE + 0.5
2
ns
Into a 50
Load
Terminated to VCC/2
tPULSE WIDTH
(2X_Q Output)
Output Pulse Width:
2X_Q @ VCC
80MHz
100MHz
133MHz
160MHz
0.5tCYCLE – 0.7
0.5tCYCLE – 0.5
0.5tCYCLE – 0.5
TBD
0.5tCYCLE + 0.7
0.5tCYCLE + 0.5
0.5tCYCLE + 0.5
TBD
ns
tPD
1
SYNC Feedback
SYNC Input to Feedback Delay
(Measured at SYNC0 or 1 and
FEEDBACK Input Pins)
(With 1M
from RC1 to An VCC)
ns
See Note
2
and
Figure 2 for Detailed
Explanation
133MHz
160MHz
–1.05
–0.9
–0.25
–0.10
tCYCLE
(2x_Q Output)
Cycle–to–Cycle Variation
133MHz
160MHz
tCYCLE – 300ps
tCYCLE – 300ps
tCYCLE + 300ps
tCYCLE + 300ps
tSKEWr
3
(Rising) See Note
4
Output–to–Output Skew Between Out-
puts Q0–Q4, Q/2 (Rising Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWf
3
(Falling)
Output–to–Output Skew Between Out-
puts Q0–Q4 (Falling Edges Only)
—
500
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tSKEWall
3
Output–to–Output Skew 2X_Q, Q/2,
Q0–Q4 Rising, Q5 Falling
—
750
ps
All Outputs Into a
Matched 50
Load
Terminated to VCC/2
tLOCK
4
Time Required to Acquire Phase–Lock
From Time SYNC Input Signal is
Received
1.0
10
ms
Also Time to LOCK
Indicator High
tPZL
5
Output Enable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
tPHZ,tPLZ
5
Output Disable Time OE/RST to 2X_Q,
Q0–Q4, Q5, and Q/2
3.0
14
ns
Measured With the
PLL_EN Pin Low
1. TCYCLE in this spec is 1/Frequency at which the particular output is running.
2. The TPD specification’s min/max values may shift closer to zero if a larger pullup resistor is used.
3. Under equally loaded conditions and at a fixed temperature and voltage.
4. With VCC fully powered–on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1
μ
F, tLOCK minimum is
with C1 = 0.01
μ
F.
5. The tPZL, tPHZ, tPLZ minimum and maximum specifications are estimates, the final guaranteed values will be available when ‘MC’ status is
reached.
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| MC88915TFN70R2 | 功能描述:IC DRIVER CLK PLL 70MHZ 28-PLCC RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MC88916 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
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