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參數(shù)資料
| 型號(hào)： | MC88916DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET |
| 中文描述： | MC88 SERIES, PLL BASED CLOCK DRIVER, 3 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | PLASTIC, SOIC-20 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 114K |
| 代理商： | MC88916DW |
MC88916
TIMING SOLUTIONS
BR1333 — REV 5
5
MOTOROLA
AC CHARACTERISTICS
(TA = –40
°
C to +85
°
C; VCC = 5.0V
±
5%)
Symbol
Parameter
Mimimum
Maximum
Unit
Condition
tRISE/FALL
1
All Outputs
Rise/Fall Time, All Outputs into a 50
Load
0.3
1.6
ns
tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
tRISE/FALL
1
2X_Q Output
Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3
0.5
1.6
ns
tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
tpulse width(a)
1
(Q0, Q1, Q2, Q3)
Output Pulse Width
Q0, Q1, Q2, Q3 at VCC/2
0.5tcycle – 0.5
0.5tcycle + 0.5
ns
50
Load Terminated to
VCC/2 (See App Note 3)
tpulse width(b)
1
(2X_Q Output)
Output Pulse Width
2X_Q at VCC/2
40–49MHz
50–65MHz
66–80MHz
0.5tcycle – 1.5
5
0.5tcycle – 1.0
5
0.5tcycle – 0.5
0.5tcycle + 1.5
5
0.5tcycle + 1.0
5
0.5tcycle + 0.5
ns
50
Load Terminated to
VCC/2 (See App Note 3)
tPD
1,4
SYNC – Q/2
SYNC Input to Q/2 Output Delay
(Measured at SYNC and Q/2 Pins)
–0.75
–0.15
ns
With 1M
From RC1
to An VCC
(See Application Note 2)
+1.25
7
+3.25
7
ns
With 1M
From RC1
to An GND
(See Application Note 2)
tSKEWr
1,2
(Rising)
Output–to–Output Skew
Between Outputs Q0–Q2, Q/2
(Rising Edge Only)
—
500
ps
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tSKEWf
1,2
(Falling)
Output–to–Output Skew
Between Outputs Q0–Q2
(Falling Edge Only)
—
1.0
ns
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tSKEWall
1,2
Output–to–Output Skew
2X_Q, Q/2, Q0–Q2 Rising
Q3 Falling
—
1.0
ns
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tLOCK
3
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
1
10
ms
tPHL MR – Q
Propagation Delay,
MR to Any Output (High–Low)
1.5
13.5
ns
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tREC, MR to
SYNC
6
Reset Recovery Time rising MR edge
to falling SYNC edge
9
—
ns
tW, MR LOW
6
Minimum Pulse Width, MR input Low
5
—
ns
tW, RST_IN LOW
Minimum Pulse Width, RST_IN Low
10
—
ns
When in Phase–Lock
tPZL
Output Enable Time
RST_IN Low to RST_OUT Low
1.5
16.5
ns
See Application
Note 5
tPLZ
Output Enable Time
RST_IN High to RST_OUT High Z
1016 ‘Q’ Cycles
(508 Q/2 Cycles)
1024 ‘Q’ Cycles
(512 Q/2 Cycles)
ns
See Application
Note 5
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1
μ
F; tLOCK Min is with C1 = 0.01
μ
F.
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Limits do not meet requirements of the 68040 microprocessor. Refer to the 88920 for a low frequency 68040 clock driver.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
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