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參數(shù)資料
| 型號： | MC88921DW |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 88921 SERIES, PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 544K |
| 代理商： | MC88921DW |
MC88921
TIMING SOLUTIONS
BR1333 — REV 5
5
MOTOROLA
AC CHARACTERISTICS (TA = –40°C to 85°C; VCC = 5.0V ± 5%)
Symbol
Parameter
Minimum
Maximum
Unit
Condition
tRISE/FALL1
All Outputs
Rise/Fall Time, All Outputs into 50
Load
0.3
1.6
ns
tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
tRISE/FALL1
2X_Q Output
Rise/Fall Time into a 20pF Load, With
Termination Specified in AppNote 3
0.5
1.6
ns
tRISE – 0.8V to 2.0V
tFALL – 2.0V to 0.8V
tpulse width(a)1
(Q0, Q1, Q2, Q3)
Output Pulse Width
Q0, Q1, Q2, Q3 at VCC/2
0.5tcycle – 0.55
0.5tcycle + 0.55
ns
50
Load Terminated to
VCC/2 (See Application
Note 3)
tpulse width(b)1
(2X_Q Output)
Output Pulse Width
2X_Q at VCC/2
0.5tcycle – 0.55
0.5tcycle + 0.55
ns
50
Load Terminated to
VCC/2 (See Application
Note 3)
tPD1,4
SYNC – Q/2
SYNC Input to Q Output Delay
(Measured at SYNC and Q/2 Pins)
–0.75
–0.15
ns
With 1M
From RC1
to An VCC
(See Application Note 2)
+1.25 7
+3.25 7
ns
With 1M
From RC1
to An GND
(See Application Note 2)
tSKEWr1,2
(Rising)
Output–to–Output Skew
Between Outputs Q0–Q3
(Rising Edge Only)
—
500
ps
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tSKEWf1,2
(Falling)
Output–to–Output Skew
Between Outputs Q0–Q3
(Falling Edge Only)
—
1.0
ns
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tSKEWall1,2
Output–to–Output Skew
2X_Q, Q0–Q3 Rising
—
1.0
ns
Into a 50
Load
Terminated to VCC/2
(See Timing Diagram in
Figure 6)
tLOCK3
Phase–Lock Acquisition Time,
All Outputs to SYNC Input
1
10
ms
tPHL MR – Q
Propagation Delay,
MR to Any Output (High–Low)
1.5
13.5
ns
Into a 50
Load
Terminated to VCC/2
tREC, MR to
SYNC6
Reset Recovery Time rising MR edge
to falling SYNC edge
9
—
ns
tREC, MR to
Normal Operation
Recovery Time for Outputs 2X_Q, Q0,
Q1 to Return to Normal PLL Operation
—
3 Clock Cycles
(Q Frequency)
ns
tW, MR LOW6
Minimum Pulse Width, MR input Low
5
—
ns
1. These specifications are not tested, they are guaranteed by statistical characterization. See Application Note 1 for a discussion of this
methodology.
2. Under equally loaded conditions and at a fixed temperature and voltage.
3. With VCC fully powered–on: tCLOCK Max is with C1 = 0.1F; tLOCK Min is with C1 = 0.01F.
4. See Application Note 4 for the distribution in time of each output referenced to SYNC.
5. Refer to Application Note 3 to translate signals to a 1.5V threshold.
6. Specification is valid only when the PLL_EN pin is low.
7. This is a typical specification only, worst case guarantees are not provided.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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MC88921
Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
NETCOM
IDT Low Skew CMOS PLL Clock Drivers With Power-Down/Power-up Feature
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC88921
5
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