參數(shù)資料
型號(hào): MC88921DW
廠商: MOTOROLA INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: LOW SKEW CMOS PLL CLOCK DRIVER With Power-Down/ Power-Up Feature
中文描述: 88921 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封裝: PLASTIC, SOIC-20
文件頁(yè)數(shù): 4/10頁(yè)
文件大?。?/td> 106K
代理商: MC88921DW
MC88921
MOTOROLA
TIMING SOLUTIONS
BR1333 — REV 5
4
Figure 1. MC88921 Logic Block Diagram
Q
R
D
Q0
VCO
CH
PUMP
PFD
SYNC1
PLL_EN
MR
POWER–ON
RESET
0
1
LOCK INDICATOR
2X_Q
LOCK
Q
R
D
Q1
Q
R
D
Q2
Q
R
D
“Dummy” Flip–Flop to Maintain
Phase–Locked Operation
Q
R
D
Q3
Q
R
D
Q
RC1
÷
2
0
1
FBSEL
Q/2
FREQUENCY SPECIFICATIONS
(TA = –40
°
C to 85
°
C; VCC = 5.0V
±
5%)
Symbol
Parameter
Guaranteed Minimum
Unit
Fmax (2X_Q)
Maximum Operating Frequency, 2X_Q Output
66
MHz
Fmax (‘Q’)
Maximum Operating Frequency,
Q0–Q3 Outputs
33
MHz
1. Maximum Operating Frequency is guaranteed with the 88921 in a phase–locked condition, and all outputs loaded at 50pF.
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