Monitor Module (MON)
MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet, Rev. 5.0
Freescale Semiconductor
247
19.3.1.1 Normal Monitor Mode
When VTST is applied to IRQ and PTC3 is low upon monitor mode entry, the bus frequency is a
divide-by-two of the input clock. If PTC3 is high with VTST applied to IRQ upon monitor mode entry, the
bus frequency will be a divide-by-four of the input clock. Holding the PTC3 pin low when entering monitor
mode causes a bypass of a divide-by-two stage at the oscillator only if VTST is applied to IRQ. In this
event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have a 50% duty cycle at maximum bus
frequency.
Table 19-1. Monitor Mode Signal Requirements and Options
Mode
IRQ
RST
Reset
Vector
Serial
Comm.
Mode Selection Divider
ICG
COP
Communication Speed
PTA0
PTC0
PTC1
PTC3
External
Clock
Bus
Frequency
Baud
Range
Normal
Monitor
VTST VDD or VSS
X
1100
OFF Disabled
4.9152
MHz
2.4576
MHz
9600
VTST VDD or VSS
X
1101
OFF Disabled
9.8304
MHz
2.4576
MHz
9600
Forced
Monitor
VDD
$FFFF
(blank)
1
X
OFF Disabled
9.8304
MHz
2.4576
MHz
9600
VSS
VDD
$FFFF
(blank)
1
X
ON Disabled
X
Nominal
2.4576
MHz
Nominal
9600
User
VDD
or VSS
VDD
or VSS
Not
$FFFF
XXX
X
Enabled
X
MON08
Function
[Pin No.]
VTST
[6]
RST
[4]
—
COM
[8]
MOD0
[12]
MOD1
[14]
DIV4
[16]
——
OSC1
[13]
——
1. PTA0 must have a pullup resistor to VDD in monitor mode.
2. Communication speed in the table is an example to obtain a baud rate of 9600.
Baud rate using external oscillator is bus frequency / 256.
3. External clock is a 4.1952 MHz or 9.8304 MHz canned oscillator on OSC1.
4. X = don’t care.
5. MON08 pin refers to P&E Microcomputer Systems’ MONOUT-Cyclone 2 by 8-pin connector.
NC
1
2
GND
NC
3
4
RST
NC
5
6
IRQ
NC
7
8
PTA0
NC
9
10
NC
11
12
PTC0
OSC1
13
14
PTC1
VDD
15
16
PTC3