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參數(shù)資料
| 型號： | MC908QL4DW |
| 廠商： | Motorola, Inc. |
| 英文描述： | Microcontrollers |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 169/222頁 |
| 文件大?。?/td> | 2861K |
| 代理商： | MC908QL4DW |
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Initialization/Application Information
MC68HC908QL4 MC68HC908QL3 MC68HC908QL2 Data Sheet, Rev. 4
Freescale Semiconductor
169
14.9.16 Oscillator Trimming with SLIC
SLCACT can be used as an indicator of LIN bus activity. SLCACT tells the user that the SLIC is currently
processing a message header (therefore synchronizing to the bus) or processing a message frame
(including checksum). Therefore, at idle times between message frames or during a message frame
which has been marked as a “don’t care” by writing IMSG, it is possible to trim the oscillator circuit of the
MCU with no impact to the LIN communications.
It is important to note the exact mechanisms with which the SLIC sets and clears SLCACT. Any falling
edge which successfully passes through the digital receive filter will cause SLCACT to become set. This
might even include noise pulses, if they are of sufficient length to pass through the digital RX filter.
Although in these cases SLCACT is becoming set on a noise spike, it is very probable that noise of this
nature will cause other system issues as well such as corruption of the message frame. The software can
then further qualify if it is appropriate to trim the oscillator.
SLCACT will only be cleared by the SLIC upon successful completion of a normal LIN message frame
(see
14.8.3 SLIC Status Register
description for more detail). This means that in some cases, if a
message frame terminates with an error condition or some source other than those cited in the SLCACT
bit description, SLCACT might remain set during an otherwise idle bus time. SLCACT will then clear upon
the successful completion of the next LIN message frame.
These mechanisms might result in SLCACT being set when it is safe (from the SLIC module perspective)
to trim the oscillator. However, SLCACT will only be clear when the SLIC considers it safe to trim the
oscillator.
In a particular system, it might also be possible to improve the opportunities for trimming by using system
knowledge and use of IMSG. If a message ID is known to be considered a “don’t care” by this particular
node, it should be safe to trim the oscillator during that message frame (provided that it is safe for the
application software as well). After the software has done an identifier lookup and determined that the ID
corresponds to a “don’t care” message, the software might choose to set IMSG. From that time, the
application software should have at least one byte time of message traffic in which to trim the oscillator
before that ignored message frame expires, regardless of the state of SLCACT. If the length of that
ignored message frame is known, that knowledge might also be used to extend the time of this oscillator
trimming opportunity.
Now that the mechanisms for recognizing when the SLIC module indicates safe oscillator trimming
opportunities are understood, it is important to understand how to derive the information needed to
perform the trimming.
The value in SLCBT will indicate how many SLIC clock cycles comprise one bit time and for any given
LIN bus speed, this will be a fixed value if the oscillator is running at its ideal frequency. It is possible to
use this ideal value combined with the measured value in SLCBT to determine how to adjust the oscillator
of the microcontroller.
The actual oscillator trimming algorithm is very specific to each particular implementation, and
applications might or might not require the oscillator even to be trimmed. The SLIC can maintain
communications even with input oscillator variation of ±50% (with 4 MHz nominal, that means that any
input clock into the SLIC from 2 MHz to 6 MHz will still guarantee communications). Because Freescale
internal oscillators are at least within ±25% of their nominal value, even when untrimmed, this means that
trimming of the oscillator is not even required for LIN communications. If the application can tolerate the
range of frequencies which might appear within this manufacturing range, then it is not necessary ever to
trim the oscillator. This can be a tremendous advantage to the customer, enabling migration to very
low-cost ROM devices which have no non-volatile memory in which to store the trim value.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC908QL4M | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC908QL4MDT | 功能描述:IC MCU 8BIT 4K FLASH 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC08 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC908QL4MDTE | 功能描述:8位微控制器 -MCU NITRON LINE EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| MC908QL4MDTE | 制造商:Freescale Semiconductor 功能描述:Microcontroller |
| MC908QL4MDTER | 功能描述:8位微控制器 -MCU NITRON LINE EPP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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