
Pulse-Width Modulator (PWM)
PWM Register Descriptions
M68HC12B Family — Rev. 4.0
Technical Data
MOTOROLA
Pulse-Width Modulator (PWM)
205
The value in each duty register determines the duty of the associated
PWM channel. When the duty value is equal to the counter value, the
output changes state. If the register is written while the channel is
enabled, the new value is held in a buffer until the counter rolls over or
the channel is disabled. Reading this register returns the most recent
value written.
If the duty register is greater than or equal to the value in the period
register, there is no duty change in state. If the duty register is set to $FF,
the output is always in the state which would normally be the state
opposite the PPOLx value.
Left-aligned output mode (CENTR = 0):
Duty cycle = [(PWDTYx
+ 1) / (PWPERx + 1)] × 100%
(PPOLx = 1)
Duty cycle = [(PWPERx
PWDTYx) / (PWPERx + 1)] × 100% (PPOLx = 0)
Center-aligned outputmode (CENTR = 1):
Duty cycle = [(PWPERx
PWDTYx) / PWPERx] × 100%
(PPOLx = 0)
Duty cycle = (PWDTYx
/ PWPERx) × 100%
(PPOLx = 1)