
Clock Functions
System Clock Frequency formulas
68HC(9)12D60 — Rev 4.0
Advance Information
MOTOROLA
Clock Functions
167
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tune-
up of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
12.7 System Clock Frequency formulas
SLWCLK = EXTALi / ( 2 x SLOW )
SLOW = 1,2,..63
SLWCLK = EXTALi
SLOW = 0
PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)
ECLK = SYSCLK / 2
XCLK = SLWCLK / 2
PCLK = SYSCLK / 2
BCLK(1) = EXTALi / 2
Boolean equations:
Bit 7
654321
Bit 0
0
SLDV5
SLDV4
SLDV3
SLDV2
SLDV1
SLDV0
RESET:
00000000
SLOW — Slow mode Divider Register
$003E
1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.