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參數(shù)資料
| 型號： | MC92300CG |
| 廠商： | Motorola, Inc. |
| 英文描述： | VITERBI Decoder for Digital TV |
| 中文描述： | 維特比譯碼數(shù)字電視 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 42K |
| 代理商： | MC92300CG |
MC92300
Rev.1.3
MOTOROLA
3
Viterbi Decoder Pin Description
SYMCLK
BITCLK
VDCLK
VDCLK_DIV2
RESET_N
VLCK
VFF
VEF
SR[2:0]
VO
VC0,VC1[2:0]
SDA
DSA[6:0]
SCL
TESTSEL,
FREF,
TESTOUT,
VCOCTL
- System Clock (input clock)
- System Clock (output clock)
- Input Clock
- VDCLK/2
- Asynchronous Reset
- Viterbi Decoder in Lock
- FIFO Full Flag
- FIFO Empty Flag
- Selected Rate
- Viterbi Decoder Output
- Soft Decision Input
- Data Bus of I
2
C-interface
- Slave Address of I
2
C-interface
- Clock Line of I
2
C-interface
VTSTI[1:0]
VTSTO
RESET_ASYNC
TEST_SE
TEST_MODE
- Test pins
- Test output
- Teset for Scan Test
- Test pin for Scan Mode
- Test pin for Scan Mode
MOTOROLA Device Test Pins:
51, 56-62, 105, 110-115, 120
(don’t connect these pins)
NOT CONNECTED Pins:
27, 33, 34, 88-94, 99-102
- APLL pins
128QFP
VDD
OVDD
VC1[2
]
OVSS
VC1[1]
OVSS
VC1[0]
OVSS
SYMCLK
OVSS
VSS
VDD
OVDD
VC0[2]
OVSS
OVSS
VC0[0
]
OVSS
OVSS
VSS
VDD
OVDD
VDCLK
OVSS
VDCLK_DIV2
OVSS
VSS
TESTSEL
FREF
TESTOUT
V
C
O
C
T
L
V
D
D
O
V
D
D
S
D
A
S
C
L
D
S
A
[
0
]
D
S
A
[
1
]
O
V
S
S
V
S
S
V
D
D
O
V
D
D
D
S
A
[
2
]
D
S
A
[
3
]
D
S
A
[
4
]
D
S
A
[
5
]
D
S
A
[
6
]
O
V
S
S
O
V
D
D
O
V
S
S
V
S
S
V
D
D
V
S
S
VDD
SR[0]
SR[1]
SR[2]
VEF
VFF
VSS
VO
OVSS
VLCK
OVDD
VSS
VDD
OVDD
OVSS
VSS
V
D
D
O
V
D
D
T
E
S
T
_
S
E
T
E
S
T
_
M
O
D
E
O
V
S
S
V
S
S
V
D
D
O
V
D
D
O
V
S
S
O
V
D
D
R
E
S
E
T
_
A
S
Y
N
C
R
E
S
E
T
_
N
V
T
S
T
I
[
0
]
V
T
S
T
I
[
1
]
V
T
S
T
O
P
E
N
I
D
O
V
S
S
V
S
S
V
S
S
V
D
D
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