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參數(shù)資料
| 型號： | MC92600ZTB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PBGA196 |
| 封裝： | 15 X 15 MM, 1.60 MM HEIGHT, 1 MM PITCH, PLASTIC, MABGA-196 |
| 文件頁數(shù)： | 31/98頁 |
| 文件大?。?/td> | 1018K |
| 代理商： | MC92600ZTB |
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MOTOROLA
Chapter 3. Receiver
3-9
Receiver Clock Timing Modes
3.4.1
Recovered Clock Timing Mode
The recovered clock signal, RECV_x_RCLK, is generated by the receiver and, on average,
runs at the reference clock frequency of the transmitter at the other end of the link. The
recovered clock is not generated by a clock recovery PLL, but is generated by the receiver
bit-accumulation and byte-alignment logic. The RECV_x_RCLK signal is asserted high,
generating a rising edge, whenever a new byte (character) is accumulated and available.
To track a transmitter frequency that is offset from the receiver’s reference clock frequency,
the duty cycle and period of the recovered clock is modulated. The MC92600 is designed
to tolerate up to +250 ppm of frequency offset. For example: if the transmitter is running
100 ppm faster than the receiver, then a short cycle is generated approximately every 2,000
received bytes. The short cycle has a period equal to eight bit-times instead of the normal
ten bit-times. This implies that logic using received data timed to the recovered clock must
be able to operate with a period equal to eight bit-times (6.4 ns for 1.25 gigabaud). Each
short cycle recovers two bit-times of offset. Generally, the number of received bytes
(characters) between short cycles is equal to:
(2 * 106) / (10 * N) bytes
where:
N is the frequency offset in ppm.
Alternately, if the transmitter is running 100 ppm slower than the receiver, then a long cycle
is generated approximately every 2,000 received bytes. The long cycle has a period equal
to twelve bit-times instead of ten bit-times. The above equation is also used to compute the
period between long cycles.
Data is timed to the rising edge of the recovered clock signal except in double data rate
mode where data is timed to the rising and falling edges of the recovered clock.
If the receivers are being operated in word synchronization mode (WSE = high), the data
for all four receivers are timed relative to link A’s recovered clock RECV_A_RCLK.
NOTE
Recovered clocks RECV_B_RCLK, RECV_C_RCLK, and
RECV_D_RCLK are not aligned to the data in word
synchronization mode and should not be used.
3.4.2
Reference Clock Timing Mode
Data is timed relative to the reference clock when RCCE is low. Synchronization between
the recovered clock and the reference clock is handled by the receiver interface. Frequency
offset between the transmitter’s reference clock and the receiver’s reference clock causes
overrun/underrun situations. Overrun occurs when the transmitter is running faster than the
receiver. Underrun occurs when the transmitter is running slower than the receiver.
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