參數(shù)資料
型號: MC9328MX21VK
廠商: Freescale Semiconductor
文件頁數(shù): 56/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝: 152
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 289-LFBGA
包裝: 托盤
Specifications
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
59
control register PST. When the PST bit is set to a one, it means that a DS2502 is present; if the bit is set to
a zero, then no device was found.
3.17.2
Write 0
The Write 0 function simply writes a zero bit to the DS2502. The sequence takes 117 us. The one-wire bus
is held low for 100us.
Figure 47. Write 0 Timing
The Write 0 pulse sequence is initiated when the WR0 control bit register is set. When the write is
complete, the WR0 register will be auto cleared.
3.17.3
Write 1/Read Data
The Write 1 and Read timing is identical. The time slot is first driven low. According to the DS2502
documentation, the DS2502 has a delay circuit which is used to synchronize the DS2502 with the bus
master (one-wire). This delay circuit is triggered by the falling edge of the data line and is used to decide
when the DS2502 should sample the line. In the case of a write 1 or read 1, after a delay, a 1 will be
transmitted / received. When a read 0 slot is issued, the delay circuit will hold the data line low to override
the 1 generated by the bus master (one-wire).
For the Write 1 or Read, the control register WR1/RD is set and auto-cleared when the sequence has been
completed. After a Read, the control register RDST bit is set to the value of the read.
Figure 48. Write 1 Timing
100us
one-wire
17us
BUS
Write 0 Slot 128us
AutoClear WR0
Set WR0
5us
Write “1” Slot 117us
Set WR1/RD
Auto Clear WR1/RD
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