參數(shù)資料
型號: MC9328MX21VKR2
廠商: Freescale Semiconductor
文件頁數(shù): 33/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX21 266MHZ 289-MAPBGA
標(biāo)準(zhǔn)包裝: 1,000
系列: i.MX21
核心處理器: ARM9
芯體尺寸: 32-位
速度: 266MHz
連通性: 1 線,EBI/EMI,I²C,IrDA,MMC,智能卡,SPI,SSI,UART/USART,USB OTG
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 192
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.45 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 289-LFBGA
包裝: 帶卷 (TR)
MC9328MX21 Technical Data, Rev. 3.4
38
Freescale Semiconductor
Specifications
Figure 27. Timing Diagrams at Data Transfer Mode
Figure 28 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay NAC, beginning
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance NAC until the card sees a stop transmission command. The
data stops two clock cycles after the end bit of the stop command.
Timing of command sequences (all modes)
Timing response end to next CMD start (data transfer mode)
Command response timing (data transfer mode)
Host Command
Response
NCR cycles
CMD
Content
S T
E Z Z P
P S T
Content
CRC E Z Z
******
CRC
Z
Response
Host Command
NRC cycles
CMD
Content
S T
E Z
Z S T
Content
CRC E Z Z
******
CRC
Z
Host Command
NCC cycles
CMD
Content
S T
E Z
Z S T
Content
CRC E Z Z
******
CRC
Z
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