參數(shù)資料
型號(hào): MC9328MXSVP10
廠商: Freescale Semiconductor
文件頁數(shù): 18/74頁
文件大?。?/td> 0K
描述: IC MCU I.MXS 100MHZ 225-MAPBGA
標(biāo)準(zhǔn)包裝: 160
系列: i.MXS
核心處理器: ARM9
芯體尺寸: 32-位
速度: 100MHz
連通性: EBI/EMI,I²C,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 97
程序存儲(chǔ)器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 225-LFBGA
包裝: 托盤
Functional Description and Application Information
MC9328MXS Technical Data, Rev. 3
Freescale Semiconductor
25
4.4.2.1
WAIT Read Cycle without DMA
Figure 6. WAIT Read Cycle without DMA
Table 13. WAIT Read Cycle without DMA: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1OE and EB assertion time
See note 2
ns
2CS5 pulse width
3T
ns
3OE negated to address inactive
56.81
57.28
ns
4
Wait asserted after OE asserted
1020T
ns
5
Wait asserted to OE negated
2T+1.57
3T+7.33
ns
6
Data hold timing after OE negated
T-1.49
ns
7
Data ready after wait asserted
0
T
ns
8
OE negated to CS negated
1.5T-0.68
1.5T-0.06
ns
9
OE negated after EB negated
0.06
0.18
ns
10
Become low after CS5 asserted
0
1019T
ns
11
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB assertion in read cycle will occur only when
EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
WAIT
Address
EB
CS5
OE
DATABUS
programmable
min 0ns
1
2
3
8
9
5
6
7
11
10
4
(input to i.MXS)
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