MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
393
Chapter 18
Debug Module (S08DBGV3) (128K)
18.1
Introduction
The DBG module implements an on-chip ICE (in-circuit emulation) system and allows non-intrusive
debug of application software by providing an on-chip trace buffer with exible triggering capability. The
trigger also can provide extended breakpoint capacity. The on-chip ICE system is optimized for the HCS08
8-bit architecture and supports 64K bytes or 128K bytes of memory space.
18.1.1
Features
The on-chip ICE system includes these distinctive features:
Three comparators (A, B, and C) with ability to match addresses in 128K space
— Dual mode, Comparators A and B used to compare addresses
— Full mode, Comparator A compares address and Comparator B compares data
— Can be used as triggers and/or breakpoints
— Comparator C can be used as a normal hardware breakpoint
— Loop1 capture mode, Comparator C is used to track most recent COF event captured into FIFO
Tag and Force type breakpoints
Nine trigger modes
—A
— A Or B
— A Then B
— A And B, where B is data (Full mode)
— A And Not B, where B is data (Full mode)
— Event Only B, store data
— A Then Event Only B, store data
— Inside Range, A
≤ Address ≤ B
— Outside Range, Address
< Α or Address > B
FIFO for storing change of ow information and event only data
— Source address of conditional branches taken
— Destination address of indirect JMP and JSR instruction
— Destination address of interrupts, RTI, RTC, and RTS instruction
— Data associated with Event B trigger modes