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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MC9S08DZ96CLF
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 301/458闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� MCU 8BIT 96K FLASH 48-LQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 250
绯诲垪锛� S08
鏍稿績铏曠悊鍣細 S08
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫i€氭€э細 CAN锛孖²C锛孡IN锛孲CI锛孲PI
澶栧湇瑷�(sh猫)鍌欙細 LVD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 39
绋嬪簭瀛樺劜鍣ㄥ閲忥細 96KB锛�96K x 8锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 2K x 8
RAM 瀹归噺锛� 6K x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 2.7 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 16x12b
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 48-LQFP
鍖呰锛� 鎵樼洡
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Chapter 2 Pins and Connections
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
37
89
57
43
VREFH
90
58
VDDA
91
鈥�
PTK4
92
鈥�
PTK5
93
鈥�
PTK6
94
鈥�
PTK7
95
59
44
PTA4
PIA4
ADP4
96
60
45
PTB4
PIB4
ADP12
97
61
鈥�
PTC4
ADP20
98
62
46
PTA5
PIA5
ADP5
99
63
47
PTB5
PIB5
ADP13
100
64
48
PTA6
PIA6
ADP6
1 Pin does not contain a clamp diode to V
DD and should not be driven above
VDD. The voltage measured on this pin when internal pull-up is enabled may
be as low as VDD - 0.7V. The internal gates connected to this pin are pulled to
VDD.
2 The IIC1 module pins can be repositioned using IIC1PS bit in the SOPT1
register. The default reset locations are on PTF2 and PTF3.
3 The SCI2 module pins can be repositioned using SCI2PS bit in the SOPT1
register. The default reset locations are on PTF0 and PTF1.
4 If both these analog modules are enabled they both will have access to the pin.
Table 2-1. Pin Availability by Package Pin-Count (continued)
Pin Number
<-- Lowest
Priority
--> Highest
100
64
48
Port
Pin/Interrupt
Alt 1
Alt 2
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
VI-BTY-IX-F2 CONVERTER MOD DC/DC 3.3V 49.5W
VI-B6B-IY-B1 CONVERTER MOD DC/DC 95V 50W
MC56F8027VLH IC DIGITAL SIGNAL CTLR 64-LQFP
VE-211-IY-F1 CONVERTER MOD DC/DC 12V 50W
VI-BVY-IX-F1 CONVERTER MOD DC/DC 3.3V 49.5W
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鍙冩暩(sh霉)鎻忚堪
MC9S08DZ96CLH 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 BIT 96K FLS 2K EEP CA RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MC9S08DZ96CLL 鍔熻兘鎻忚堪:8浣嶅井鎺у埗鍣� -MCU 8 BIT 96K FLS 2K EEP CA RoHS:鍚� 鍒堕€犲晢:Silicon Labs 鏍稿績:8051 铏曠悊鍣ㄧ郴鍒�:C8051F39x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:8 bit 鏈€澶ф檪閻橀牷鐜�:50 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:16 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:1 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:1.8 V to 3.6 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:QFN-20 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MC9S08DZ96F2CLF 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Microcontrollers
MC9S08DZ96F2CLH 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Microcontrollers
MC9S08DZ96F2CLL 鍒堕€犲晢:FREESCALE 鍒堕€犲晢鍏ㄧū:Freescale Semiconductor, Inc 鍔熻兘鎻忚堪:Microcontrollers