參數資料
型號： MC9S08FL16CBM
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP32
封裝： ROHS COMPLIANT, PLASTIC, SDIP-32
文件頁數： 15/34頁
文件大?。?/td> 464K
代理商： MC9S08FL16CBM
MC9S08FL16 Series Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
22
5.9.1
Control Timing
Figure 12. Reset Timing
Table 10. Control Timing
Num
C
Rating
Symbol
Min
Typical1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 C unless otherwise stated.
Max
Unit
1D
Bus frequency (tcyc = 1/fBus)fBus
dc
—
10
MHz
2
D
Internal low power oscillator period
tLPO
700
—
1300
s
3D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst
100
—
ns
4
D
Reset low drive
trstdrv
34
t
cyc
——
ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
—
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes3
3 To enter BDM mode following a POR, BKGD/MS must be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
—
s
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH, tIHIL
100
1.5
t
cyc
—
ns
8D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5
t
cyc
—
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 C to 85 C.
tRise, tFall
—
16
23
—
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
5
9
—
ns
textrst
RESET PIN
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