參數(shù)資料
型號: MC9S08MM128VMB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 48 MHz, MICROCONTROLLER, PBGA81
封裝: 10 X 10 MM, 1.60 MM HEIGHT, ROHS COMPLIANT, PLASTIC, BGA-81
文件頁數(shù): 32/50頁
文件大?。?/td> 970K
代理商: MC9S08MM128VMB
Preliminary Electrical Characteristics
Freescale Semiconductor
38
2.12
SPI Characteristics
Table 21 and Figure 12 through Figure 15 describe the timing requirements for the SPI system.
Table 21. SPI Timing
No.1
1 Numbers in this column identify elements in Figure 12 through Figure 15.
Characteristic2
2 All timing is shown with respect to 20% V
DD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
Symbol
Min
Max
Unit
C
1
Operating frequency
Master
Slave
fop
fBus/2048
0
fBus/2
fBus/4
Hz
D
2
SPSCK period
Master
Slave
tSPSCK
2
4
2048
tcyc
D
3
Enable lead time
Master
Slave
tLead
1
/2
1
tSPSCK
tcyc
D
4
Enable lag time
Master
Slave
tLag
1
/2
1
tSPSCK
tcyc
D
5
Clock (SPSCK) high or low time
Master
Slave
tWSPSCK
tcyc – 30
1024 tcyc
ns
D
6
Data setup time (inputs)
Master
Slave
tSU
15
ns
D
7
Data hold time (inputs)
Master
Slave
tHI
0
25
ns
D
8
Slave access time3
3 Time to data active from high-impedance state.
ta
—1
tcyc
D
9
Slave MISO disable time4
4 Hold time to high-impedance state.
tdis
—1
tcyc
D
10
Data valid (after SPSCK edge)
Master
Slave
tv
25
ns
D
11
Data hold time (outputs)
Master
Slave
tHO
0
ns
D
12
Rise time
Input
Output
tRI
tRO
tcyc – 25
25
ns
D
13
Fall time
Input
Output
tFI
tFO
tcyc – 25
25
ns
D
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC9S08MM128
products
in
81
MAPBGA
packages
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