參數(shù)資料
型號(hào): MC9S08QA4CFQE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: MICROCONTROLLER, DSO8
封裝: 4 X 4 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, DFN-8
文件頁(yè)數(shù): 5/32頁(yè)
文件大?。?/td> 2368K
代理商: MC9S08QA4CFQE
Electrical Characteristics
MC9S08QA4 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
13
3.8.1
Control Timing
Figure 9. Typical RTI Clock Period vs. Temperature
Table 9. Control Timing
Parameter
Symbol
Min
Typical1
1 Data in Typical column was characterized at 3.0 V, 25
°C.
Max
Unit
Bus frequency (tcyc = 1/fBus)fBus
0—
10
MHz
Real-time interrupt internal oscillator period (see Table 9)
tRTI
700
1000
1300
μs
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized.
textrst
100
ns
IRQ pulse width
Asynchronous path2
Synchronous path3
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH
100
1.5 tcyc
——
ns
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, tIHIL
100
1.5 tcyc
——
ns
Port rise and fall time (load = 50 pF)4
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40°C to 85°C.
tRise, tFall
3
30
ns
BKGD/MS setup time after issuing background debug force
reset to enter user or BDM modes
tMSSU
500
ns
BKGD/MS hold time after issuing background debug force
reset to enter user or BDM modes5
5 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
μs
–40
0
20
40
60
80
100
1600
1400
1200
1000
800
600
400
200
0
Temperature (
°C)
Period (
μs)
= +3
σ
= –3
σ
= Mean
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參數(shù)描述
MC9S08QA4CFQEE 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Technical Data
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