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參數(shù)資料
| 型號(hào)： | MC9S08QE128CQD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 50.33 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 2 MM, HEIGHT, 0.80 MM PITCH, QFP-44 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大小： | 834K |
| 代理商： | MC9S08QE128CQD |
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Electrical Characteristics
MC9S08QE128 Series Advance Information Data Sheet, Rev. 3
Freescale Semiconductor
23
Figure 15. Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V)
8C
Total deviation of trimmed DCO output frequency over voltage
and temperature
Δfdco_t
—
+ 0.5
-1.0
± 2
%fdco
9C
Total deviation of trimmed DCO output frequency over xed
voltage and temperature range of 0
°C to 70 °C
Δfdco_t
—
± 0.5
± 1
%fdco
10
C
FLL acquisition time 3
tAcquire
——
1
ms
11
C
Long term jitter of DCO output clock (averaged over 2-ms interval)
4
CJitter
—
0.02
0.2
%fdco
1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
2 The resulting bus clock frequency should not exceed the maximum specied bus clock frequency of the device.
3 This specication applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specication assumes it is already running.
4 Jitter is the average deviation from the programmed frequency measured over the specied interval at maximum f
Bus.
Measurements are made with the device powered by ltered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a
given interval.
Table 11. ICS Frequency Specications (Temperature Range = –40 to 85
°C Ambient) (continued)
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
TBD
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