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| 型號(hào)： | MC9S08RC60CFJE |
| 廠商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 49/234頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 60K FLASH 8MHZ 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,250 |
| 系列： | S08 |
| 核心處理器： | S08 |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SCI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 25 |
| 程序存儲(chǔ)器容量： | 60KB（60K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-LQFP |
| 包裝： | 托盤(pán) |
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Timer/PWM (TPM)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
142
Freescale Semiconductor
10.7.4
Timer Channel n Status and Control Register (TPM1CnSC)
TPM1CnSC contains the channel interrupt status ag and control bits that are used to congure the
interrupt enable, channel conguration, and pin function.
76543210
R
CHnF
CHnIE
MSnB
MSnA
ELSnB
ELSnA
00
W
Reset
00000000
= Unimplemented or Reserved
Figure 10-10. Timer Channel n Status and Control Register (TPM1CnSC)
Table 10-4. TPM1CnSC Register Field Descriptions
Field
Description
7
CHnF
Channel n Flag — When channel n is congured for input capture, this ag bit is set when an active edge occurs
on the channel n pin. When channel n is an output compare or edge-aligned PWM channel, CHnF is set when
the value in the TPM counter registers matches the value in the TPM channel n value registers. This ag is
seldom used with center-aligned PWMs because it is set every time the counter matches the channel value
register, which correspond to both edges of the active duty cycle period.
A corresponding interrupt is requested when CHnF is set and interrupts are enabled (CHnIE = 1). Clear CHnF
by reading TPM1CnSC while CHnF is set and then writing a 0 to CHnF. If another interrupt request occurs before
the clearing sequence is complete, the sequence is reset so CHnF would remain set after the clear sequence
was completed for the earlier CHnF. This is done so a CHnF interrupt request cannot be lost by clearing a
previous CHnF. Reset clears CHnF. Writing a 1 to CHnF has no effect.
0 No input capture or output compare event occurred on channel n
1 Input capture or output compare event occurred on channel n
6
CHnIE
Channel n Interrupt Enable — This read/write bit enables interrupts from channel n. Reset clears CHnIE.
0 Channel n interrupt requests disabled (use software polling)
1 Channel n interrupt requests enabled
5
MSnB
Mode Select B for TPM Channel n — When CPWMS = 0, MSnB = 1 congures TPM channel n for
edge-aligned PWM mode. For a summary of channel mode and setup controls, refer to Table 10-5.
4
MSnA
Mode Select A for TPM Channel n — When CPWMS = 0 and MSnB = 0, MSnA congures TPM channel n for
input capture mode or output compare mode. Refer to Table 10-5 for a summary of channel mode and setup
controls.
3:2
ELSn[B:A]
Edge/Level Select Bits — Depending on the operating mode for the timer channel as set by
CPWMS:MSnB:MSnA and shown in Table 10-5, these bits select the polarity of the input edge that triggers an
input capture event, select the level that will be driven in response to an output compare match, or select the
polarity of the PWM output.
Setting ELSnB:ELSnA to 0:0 congures the related timer pin as a general-purpose I/O pin unrelated to any timer
channel functions. This function is typically used to temporarily disable an input capture channel or to make the
timer pin available as a general-purpose I/O pin when the associated timer channel is set up as a software timer
that does not require the use of a pin. This is also the setting required for channel 0 when the TPM1CH0 pin is
used as an external clock input.
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| VI-B1V-CU-F2 | CONVERTER MOD DC/DC 5.8V 200W |
| MC9S08RC60CFGE | IC MCU 60K FLASH 8MHZ 44-LQFP |
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| MC9S08RC60CPE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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| MC9S08RC60FG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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