
Carrier Modulator Transmitter (CMT) Block Description
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
113
Figure 8-4. Modulator Block Diagram
8.5.2.1
Time Mode
When the modulator operates in time mode (MCGEN bit is set, BASE bit is clear, and FSK bit is clear),
the modulation mark period consists of an integer number of CMTCLK
÷ 8 clock periods. The modulation
space period consists of zero or an integer number of CMTCLK
÷ 8 clock periods. With an 8 MHz bus and
CMTDIV1:CMTDIV0 = 00, the modulator resolution is 1
s and has a maximum mark and space period
of about 65.535 ms each. See
Figure 8-5 for an example of the time mode and baseband mode outputs.
The mark and space time equations for time and baseband mode are:
tmark = (CMTCMD1:CMTCMD2 + 1) ÷ (fCMTCLK ÷ 8)
Eqn. 8-5
tspace = CMTCMD3:CMTCMD4 ÷ (fCMTCLK ÷ 8)
Eqn. 8-6
where CMTCMD1:CMTCMD2 and CMTCMD3:CMTCMD4 are the decimal values of the concatenated
registers.
NOTE
If the modulator is disabled while the tmark time is less than the programmed
carrier high time (tmark < CMTCGH1/fCMTCLK), the modulator can enter
into an illegal state and end the curent cycle before the programmed value.
Make sure to program tmark greater than the carrier high time to avoid this
illegal state.
=?
0
COUNTER
CMTCLOCK
CMTCMD1:CMTCMD2
CMTCMD3:CMTCMD4
SPACE PERIOD REGISTER *
17-BIT DOWN COUNTER *
* DENOTES HIDDEN REGISTER
16 BITS
MS
BIT
16
MODULE INTERRUPT REQUEST
÷ 8
CLOCK CONTROL
CARRIER OUT (fCG)
LOAD
SYSTEM CONTROL
EOC FLAG SET
MODULATOR GATE
OUT
PRIMARY/SECONDARY SELECT
.
MODULATOR
EXSPC
MODE
EOCIE
BASE
FSK