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參數(shù)資料
| 型號： | MC9S08RD32FDE |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC48 |
| 封裝： | 7 X 7 MM, 1 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220VKKD-2, TQFN-48 |
| 文件頁數(shù)： | 189/234頁 |
| 文件大?。?/td> | 1758K |
| 代理商： | MC9S08RD32FDE |
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Resets, Interrupts, and System Conguration
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
58
Freescale Semiconductor
The MC9S08RC/RD/RE/RG has these sources for reset:
Power-on reset (POR)
Low-voltage detect (LVD)
Computer operating properly (COP) timer
Illegal opcode detect
Illegal address (16K and 8K devices only)
Background debug forced reset
The reset pin (RESET)
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register. Whenever the MCU enters reset, the reset pin is driven low for 34 internal
bus cycles where the internal bus frequency is one-half the OSC frequency. After the 34 cycles are
completed, the pin is released and will be pulled up by the internal pullup resistor, unless it is held low
externally. After the pin is released, it is sampled after another 38 cycles to determine whether the reset pin
is the cause of the MCU reset.
5.4
Computer Operating Properly (COP) Watchdog
The COP watchdog is intended to force a system reset when the application software fails to execute as
expected. To prevent a system reset from the COP timer (when it is enabled), application software must
reset the COP timer periodically. If the application program gets lost and fails to reset the COP before it
times out, a system reset is generated to force the system back to a known starting point. The COP
watchdog is enabled by the COPE bit in SOPT (see Section 5.8.4, “System Options Register (SOPT),” for
additional information). The COP timer is reset by writing any value to the address of SRS. This write does
not affect the data in the read-only SRS. Instead, the act of writing to this address is decoded and sends a
reset signal to the COP timer.
After any reset, the COP timer is enabled. This provides a reliable way to detect code that is not executing
as intended. If the COP watchdog is not used in an application, it can be disabled by clearing the COPE
bit in the write-once SOPT register. Also, the COPT bit can be used to choose one of two timeout periods
(218 or 220 cycles of the bus rate clock). Even if the application will use the reset default settings in COPE
and COPT, the user must write to write-once SOPT during reset initialization to lock in the settings. That
way, they cannot be changed accidentally if the application program gets lost.
The write to SRS that services (clears) the COP timer must not be placed in an interrupt service routine
(ISR) because the ISR could continue to be executed periodically even if the main application program
fails.
When the MCU is in active background mode, the COP timer is temporarily disabled.
5.5
Interrupts
Interrupts provide a way to save the current CPU status and registers, execute an interrupt service routine
(ISR), and then restore the CPU status so processing resumes where it was before the interrupt. Other than
the software interrupt (SWI), which is a program instruction, interrupts are caused by hardware events such
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC9S08RD32FG | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC9S08RD32FGE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RD32FJ | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Microcontrollers |
| MC9S08RD32FJE | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RD32PE | 功能描述:8位微控制器 -MCU AQUILA LEADFREE PDIP RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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