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| 型號(hào)： | MC9S08RG60CFG |
| 廠(chǎng)商： | Freescale Semiconductor |
| 文件頁(yè)數(shù)： | 190/234頁(yè) |
| 文件大小： | 0K |
| 描述： | IC MCU 60K FLASH 8MHZ 44LQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | S08 |
| 核心處理器： | S08 |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 39 |
| 程序存儲(chǔ)器容量： | 60KB（60K x 8） |
| 程序存儲(chǔ)器類(lèi)型： | 閃存 |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-LQFP |
| 包裝： | 托盤(pán) |
| 配用： | DEMO9S08RG60E-ND - BOARD DEMO S08RG/RC/RD/RE FAMILY |
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Resets, Interrupts, and System Conguration
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
59
as an edge on the IRQ pin or a timer-overow event. The debug module can also generate an SWI under
certain circumstances.
If an event occurs in an enabled interrupt source, an associated read-only status ag will become set. The
CPU will not respond until and unless the local interrupt enable is a logic 1 to enable the interrupt. The I
bit in the CCR is logic 0 to allow interrupts. The global interrupt mask (I bit) in the CCR is initially set
after reset, which masks (prevents) all maskable interrupt sources. The user program initializes the stack
pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts.
When the CPU receives a qualied interrupt request, it completes the current instruction before responding
to the interrupt. The interrupt sequence uses the same cycle-by-cycle sequence as the SWI instruction and
consists of:
Saving the CPU registers on the stack
Setting the I bit in the CCR to mask further interrupts
Fetching the interrupt vector for the highest-priority interrupt that is currently pending
Filling the instruction queue with the rst three bytes of program information starting from the
address fetched from the interrupt vector locations
While the CPU is responding to the interrupt, the I bit is automatically set to avoid the possibility of another
interrupt interrupting the ISR itself (this is called nesting of interrupts). Normally, the I bit is restored to 0
when the CCR is restored from the value stacked on entry to the ISR. In rare cases, the I bit may be cleared
inside an ISR (after clearing the status ag that generated the interrupt) so that other interrupts can be
serviced without waiting for the rst service routine to nish. This practice is not recommended for anyone
other than the most experienced programmers because it can lead to subtle program errors that are difcult
to debug.
The interrupt service routine ends with a return-from-interrupt (RTI) instruction that restores the CCR, A,
X, and PC registers to their pre-interrupt values by reading the previously saved information off the stack.
NOTE
For compatibility with the M68HC08 Family, the H register is not
automatically saved and restored. It is good programming practice to push
H onto the stack at the start of the interrupt service routine (ISR) and restore
it just before the RTI that is used to return from the ISR.
If two or more interrupts are pending when the I bit is cleared, the highest priority source is serviced rst
(see Table 5-1).
5.5.1
Interrupt Stack Frame
Figure 5-1 shows the contents and organization of a stack frame. Before the interrupt, the stack pointer
(SP) points at the next available byte location on the stack. The current values of CPU registers are stored
on the stack starting with the low-order byte of the program counter (PCL) and ending with the CCR. After
stacking, the SP points at the next available location on the stack, which is the address that is one less than
the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the
main program that would have executed next if the interrupt had not occurred.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 1-6278414-0 | MT-RJ WRKST JACK KIT VIOLET |
| MC68HC908GZ60VFU | IC MCU 60K FLASH 8MHZ 64QFP |
| MC68HC908GZ60MFA | IC MCU 60K FLASH 8MHZ 48LQFP |
| MC68HC908GZ60CFU | IC MCU 60K FLASH 8MHZ 64QFP |
| MC68HC908GZ60CFJ | IC MCU 60K FLASH 8MHZ 32LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9S08RG60CFGE | 功能描述:8位微控制器 -MCU 9S08 2K RAM 60K RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC9S08RG60CFJ | 功能描述:IC MCU 60K FLASH 8MHZ 32LQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:S08 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類(lèi)型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤(pán) 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| MC9S08RG60CFJE | 功能描述:8位微控制器 -MCU 9S08 2K RAM 60K FLASH RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| MC9S08RG60CFJER | 制造商:Freescale Semiconductor 功能描述:9S08 2K RAM 60K FLASH - Tape and Reel |
| MC9S08RG60CPE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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