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參數(shù)資料
| 型號(hào)： | MC9S08RG60CFJER |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, MS-026BBA, LQFP-32 |
| 文件頁(yè)數(shù)： | 70/234頁(yè) |
| 文件大?。?/td> | 1758K |
| 代理商： | MC9S08RG60CFJER |
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Serial Communications Interface (S08SCIV1)
MC9S08RC/RD/RE/RG Data Sheet, Rev. 1.11
Freescale Semiconductor
161
SCI1D. After IDLE has been cleared, it cannot become set again until the receiver has received at least one
new character and has set RDRF.
If the associated error was detected in the received character that caused RDRF to be set, the error ags —
noise ag (NF), framing error (FE), and parity error ag (PF) — get set at the same time as RDRF. These
ags are not set in overrun cases.
If RDRF was already set when a new character is ready to be transferred from the receive shifter to the
receive data buffer, the overrun (OR) ag gets set instead and the data and any associated NF, FE, or PF
condition is lost.
12.3.5
Additional SCI Functions
The following sections describe additional SCI functions.
12.3.5.1
8- and 9-Bit Data Modes
The SCI system (transmitter and receiver) can be congured to operate in 9-bit data mode by setting the
M control bit in SCI1C1. In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data
register. For the transmit data buffer, this bit is stored in T8 in SCI1C3. For the receiver, the ninth bit is
held in R8 in SCI1C3.
For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCI1D.
If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character,
it is not necessary to write to T8 again. When data is transferred from the transmit data buffer to the
transmit shifter, the value in T8 is copied at the same time data is transferred from SCI1D to the shifter.
9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the
ninth bit. Or it is used with address-mark wakeup so the ninth data bit can serve as the wakeup bit. In
custom protocols, the ninth bit can also serve as a software-controlled marker.
12.3.5.2
Stop Mode Operation
During all stop modes, clocks to the SCI module are halted.
In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these
two stop modes.
No SCI module registers are affected in stop3 mode.
Because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3
mode). Software should ensure stop mode is not entered while there is a character being transmitted out of
or received into the SCI module.
12.3.5.3
Loop Mode
When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or
single-wire mode (RSRC = 1). Loop mode is sometimes used to check software, independent of
connections in the external system, to help isolate system problems. In this mode, the transmitter output is
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC9S08RC8CFGE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
| MC9S08RC32DWE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO28 |
| MC9S08RC60FDE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, QCC48 |
| MC9S08RE60DWE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO28 |
| MC9S08RC60CFGE | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC9S08RG60CPE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RG60DWE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RG60FDE | 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC9S08RG60FG | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9S08RG60FGE | 功能描述:8位微控制器 -MCU 9S08 2K RAM 60K RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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