參數(shù)資料
型號： MC9S08SE8MRLE
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDIP28
封裝： ROHS COMPLIANT, PLASTIC, DIP-28
文件頁數(shù)： 18/38頁
文件大?。?/td> 2486K
代理商： MC9S08SE8MRLE
Electrical Characteristics
MC9S08SE8 Series MCU Data Sheet, Rev. 3
Freescale Semiconductor
25
3.10
AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1
Control Timing
Figure 19. Reset Timing
Table 13. Control Timing
Num
C
Rating
Symbol
Min
Typical1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 °C unless otherwise stated.
Max
Unit
1
D
Bus frequency (tcyc = 1/fBus)fBus
DC
—
10
MHz
2
D
Internal low power oscillator period
tLPO
700
—
1300
μs
3
D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
textrst
100
—
ns
4
D
Reset low drive3
3 When any reset is initiated, internal circuitry drives the reset pin (if enabled, RSTPE = 1) low for about 34 cycles of t
cyc.
trstdrv
34
× t
cyc
——
ns
5D
BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes
tMSSU
500
—
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes4
4 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
—
μs
7
D
IRQ pulse width
Asynchronous path2
Synchronous path5
5 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
tILIH, tIHIL
100
1.5
× t
cyc
——
ns
8D
Pin interrupt pulse width
Asynchronous path2
Synchronous path5
tILIH, tIHIL
100
1.5
× t
cyc
——
ns
9
C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
6 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 125 °C.
tRise, tFall
—
40
75
—ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
11
35
—ns
textrst
RESET PIN
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