Chapter 10 Inter-Integrated Circuit (S08IICV2)
MC9S08SG32 Data Sheet, Rev. 7
160
Freescale Semiconductor
Figure 10-9. IIC Bus Transmission Signals
10.4.1.1
Start Signal
When the bus is free, no master device is engaging the bus (SCL and SDA lines are at logical high), a
master may initiate communication by sending a start signal. As shown in
Figure 10-9, a start signal is
dened as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of a new
data transfer (each data transfer may contain several bytes of data) and brings all slaves out of their idle
states.
10.4.1.2
Slave Address Transmission
The rst byte of data transferred immediately after the start signal is the slave address transmitted by the
master. This is a seven-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted by the master responds by sending
back an acknowledge bit. This is done by pulling the SDA low at the ninth clock (see
Figure 10-9).No two slaves in the system may have the same address. If the IIC module is the master, it must not transmit
an address equal to its own slave address. The IIC cannot be master and slave at the same time. However,
if arbitration is lost during an address cycle, the IIC reverts to slave mode and operates correctly even if it
is being addressed by another master.
SCL
SDA
Start
Signal
Ack
Bit
1
23
4567
8
msb
lsb
1
23
4567
8
msb
lsb
Stop
Signal
No
SCL
SDA
1
23
456
7
8
msb
lsb
12
5
6
7
8
msb
lsb
Repeated
34
99
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
XXX
D7
D6
D5
D4
D3
D2
D1
D0
Calling Address
Read/
Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address
Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write