參數(shù)資料
型號: MC9S08SV8CBM
廠商: Freescale Semiconductor
文件頁數(shù): 16/40頁
文件大?。?/td> 0K
描述: MCU 8BIT 8K FLASH 32-SDIP
標(biāo)準(zhǔn)包裝: 17
系列: S08
核心處理器: S08
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 30
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-SDIP(0.400",10.16mm)
包裝: 管件
Electrical Characteristics
MC9S08SV16 Series Data Sheet, Rev. 2
Freescale Semiconductor
23
5.9
AC Characteristics
This section describes timing characteristics for each peripheral system.
5.9.1
Control Timing
Figure 17. Reset Timing
Table 10. Control Timing
Num
C
Rating
Symbol
Min
Typical1
1 Typical values are based on characterization data at V
DD = 5.0 V, 25 °C unless otherwise stated.
Max
Unit
1D
Bus frequency (tcyc = 1/fBus)fBus
dc
20
MHz
2
D
Internal low power oscillator period
tLPO
700
1300
μs
3D
External reset pulse width2
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
textrst
100
ns
4
D
Reset low drive
trstdrv
34
× t
cyc
——
ns
5D
BKGD/MS setup time after issuing background debug
force reset to enter user or BDM modes
tMSSU
500
ns
6D
BKGD/MS hold time after issuing background debug
force reset to enter user or BDM modes 3
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t
MSH after VDD
rises above VLVD.
tMSH
100
μs
7D
IRQ pulse width
Asynchronous path2
Synchronous path4
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
tILIH, tIHIL
100
1.5
× t
cyc
ns
8
D
Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5
× t
cyc
ns
9C
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
5 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 85 °C.
tRise, tFall
16
23
ns
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
5
9
ns
textrst
RESET PIN
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