參數(shù)資料
型號： MC9S12C32CPB25
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP52
封裝： LQFP-52
文件頁數(shù)： 98/136頁
文件大小： 2022K
代理商： MC9S12C32CPB25
Device User Guide — 9S12C128DGV1/D V01.05
64
2.4.4 VDDA, VSSA — Power Supply Pins for ATD and VREG
VDDA, VSSA are the power supply and ground input pins for the voltage regulator reference and the
analog to digital converter.
2.4.5 VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
2.4.6 VDDPLL, VSSPLL — Power Supply Pins for PLL
Provides operating voltage and ground for the Oscillator and the Phased-Locked Loop. This allows the
supply voltage to the Oscillator and PLL to be bypassed independently. This 2.5V voltage is generated by
the internal voltage regulator.
Table 2-2 MC9S12C-Family Power and Ground Connection Summary
NOTE:All VSS pins must be connected together in the application. Because fast signal transitions
place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on MCU pin load.
Section 3 System Clock Description
Mnemonic
Nominal
Voltage
Description
VDD1
VDD2
2.5 V
Internal power and ground generated by internal regulator. These also
allow an external source to supply the core VDD/VSS voltages and bypass
the internal voltage regulator.
In the 48 and 52 LQFP packages VDD2 and VSS2 are not available.
VSS1
VSS2
0V
VDDR
5.0 V
External power and ground, supply to internal voltage regulator.
VSSR
0 V
VDDX
5.0 V
External power and ground, supply to pin drivers.
VSSX
0 V
VDDA
5.0 V
Operating voltage and ground for the analog-to-digital converters and the
reference for the internal voltage regulator, allows the supply voltage to the
A/D to be bypassed independently.
VSSA
0 V
VRH
5.0 V
Reference voltage low for the ATD converter.
In the 48 and 52 LQFP packages VRL is bonded to VSSA.
VRL
0 V
VDDPLL
2.5 V
Provides operating voltage and ground for the Phased-Locked Loop. This
allows the supply voltage to the PLL to be bypassed independently.
Internal power and ground generated by internal regulator.
VSSPLL
0 V
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